參數(shù)資料
型號(hào)： MC68HSC05C4AFN
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PQCC44
封裝： PLASTIC, LCC-44
文件頁數(shù)： 32/156頁
文件大?。?/td> 992K
代理商： MC68HSC05C4AFN
Electrical Specifications
3.3 V Serial Peripheral Interface Timing
MC68HC05C4A — Rev. 4.0
General Release Specification
Electrical Specifications
127
NON-DISCLOSURE
AGREEMENT
REQUIRED
13.12 3.3 V Serial Peripheral Interface Timing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
f
OP
(M)
f
OP
(S)
dc
0.5
1.0
f
OP
MHz
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2.0
1.0
—
tcyc
s
2
Enable Lead Time
Master
Slave
tLead(M)
tLead(S)
500
—
ns
3
Enable Lag Time
Master
Slave
t
LAG
(M)
t
LAG
(S)
1.5
—
ns
s
4
Clock (SCK) High Time
Master
Slave
t
W
(SCKH)M
t
W
(SCKH)S
720
400
—
ns
5
Clock (SCK) Low Time
Master
Slave
t
W
(SCKL)M
t
W
(SCKL)S
720
400
—
ns
6
Data Setup Time (Inputs)
Master
Slave
t
SU
(M)
t
SU
(S)
200
—
ns
7
Data Hold Time (Inputs)
Master
Slave
t
H
(M)
t
H
(S)
200
—
ns
8
Slave Access Time
(Time to Data Active from High-Impedance State)
tA
0
250
ns
9
Slave Disable Time (Hold Time to High-Impedance State)
t
DIS
—
500
ns
10
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)
t
V
(M)
t
V
(S)
0.25
—
500
tcyc(M)
ns
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
t
HO
(M)
t
HO
(S)
0.25
0
—
tcyc(M)
ns
12
Rise Time (20% VDD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
RM
t
RS
—
200
2.0
ns
s
13
Fall Time (70% VDD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
FM
t
FS
—
200
2.0
ns
s
* VDD = 3.3 Vdc 0.3 Vdc;V SS = 0 Vdc, TA = TL to TH. Refer to Section 8. Timer for timing diagrams.
Signal production depends on software.
Assumes 200 pF load on all SPI pins
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