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  • 參數(shù)資料
    型號: MC68HSC05C12AP
    廠商: MOTOROLA INC
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP40
    封裝: PLASTIC, DIP-40
    文件頁數(shù): 121/156頁
    文件大小: 756K
    代理商: MC68HSC05C12AP
    Serial Communications Interface (SCI)
    SCI Operation
    MC68HC05C12A Rev. 3.0
    General Release Specification
    MOTOROLA
    Serial Communications Interface (SCI)
    67
    NON-DISCLOSURE
    AGREEMENT
    REQUIRED
    9.5.1.3 Break Characters
    Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
    break character. A break character contains all logic 0s and has no start
    and stop bits. Break character length depends on the M bit in SCCR1.
    As long as SBK is at logic one, transmitter logic continuously loads break
    characters into the shift register. After software clears the SBK bit, the
    shift register finishes transmitting the last break character and then
    transmits at least one logic 1. The automatic logic 1 at the end of a break
    character is to guarantee the recognition of the start bit of the next
    character.
    9.5.1.4 Idle Characters
    An idle character contains all logic 1s and has no start or stop bits. Idle
    character length depends on the M bit in SCCR1. The preamble is a
    synchronizing idle character that begins every transmission.
    Clearing the TE bit during a transmission relinquishes the PD1/TDO pin
    after the last character to be transmitted is shifted out. The last character
    may already be in the shift register, or waiting in the SCDR, or in a break
    character generated by writing to the SBK bit. Toggling TE from logic 0
    to logic 1 while the last character is in transmission generates an idle
    character (a preamble) that allows the receiver to maintain control of the
    PD1/TDO pin.
    9.5.1.5 Transmitter Interrupts
    Two sources can generate SCI transmitter interrupt requests:
    1. Transmit Data Register Empty (TDRE) — The TDRE bit in the
    SCSR indicates that the SCDR has transferred a character to the
    transmit shift register. TDRE is a source of SCI interrupt requests.
    The transmission complete interrupt enable bit (TCIE) in SCCR2
    is the local mask for TDRE interrupts.
    2. Transmission Complete (TC) — The TC bit in the SCSR indicates
    that both the transmit shift register and the SCDR are empty and
    that no break or idle character has been generated. TC is a source
    of SCI interrupt requests. The transmission complete interrupt
    enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.
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