參數(shù)資料
型號： MC68HSC05C12AB
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4.1 MHz, MICROCONTROLLER, PDIP42
封裝： PLASTIC, SDIP-42
文件頁數(shù)： 31/156頁
文件大?。?/td> 756K
代理商： MC68HSC05C12AB
NON-DISCLOSURE
AGREEMENT
REQUIRED
Electrical Specications
General Release Specification
MC68HC05C12A — Rev. 3.0
126
Electrical Specifications
MOTOROLA
13.11 5.0 V Serial Peripheral Interface Timing
Num
Characteristic
Symbol
Min
Max
Unit
Operating Frequency
Master
Slave
fop(M)
fop(S)
dc
0.5
2.1
fop
MHz
1
Cycle Time
Master
Slave
tcyc(M)
tcyc(S)
2.0
480
—
tcyc
ns
2
Enable Lead Time
Master
Slave
tLead(M)
tLead(S)
240
—
ns
3
Enable Lag Time
Master
Slave
t
L
ag(M)
t
L
ag(S)
720
—
ns
4
Clock (SCK) High Time
Master
Slave
tW(SCKH)M
tW(SCKH)S
340
190
—
ns
5
Clock (SCK) Low Time
Master
Slave
tW(SCKL)M
tW(SCKL)S
340
190
—
ns
6
Data Setup Time (Inputs)
Master
Slave
tSU(M)
tSU(S)
100
—
ns
7
Data Hold Time (Inputs)
Master
Slave
tH(M)
tH(S)
100
—
ns
8
Slave Access Time
(Time to Data Active from High-Impedance State)
tA
0
120
ns
9
Slave Disable Time (Hold Time to High-Impedance State)
tDIS
—
240
ns
10
Data Valid
Master (Before Capture Edge)
Slave (After Enable Edge)
tV(M)
tV(S)
0.25
—
240
tcyc(M)
ns
11
Data Hold Time (Outputs)
Master (After Capture Edge)
Slave (After Enable Edge)
tHO(M)
tHO(S)
0.25
0
—
tcyc(M)
ns
12
Rise Time (20% V
DD to 70% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tRM
tRS
—
100
2.0
ns
s
13
Fall Time (70% V
DD to 20% VDD, CL = 200 pF)
SPI Outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
tFM
tFS
—
100
2.0
ns
s
*VDD = 5.0 Vdc ± 10%; VSS = 0 Vdc, TA = TL to TH. Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
Signal production depends on software.
Assumes 200 pF load on all SPI pins
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