參數(shù)資料
型號： MC68HRC705J1ACDWR2
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 143/162頁
文件大?。?/td> 1517K
代理商： MC68HRC705J1ACDWR2
Low-Power Modes
Effects of Stop and Wait Modes
MC68HC705J1A — Rev. 3.0
Technical Data
MOTOROLA
Low-Power Modes
81
After exit from stop mode by reset:
The COP watchdog counter immediately begins counting from
$0000.
The COP watchdog counter is cleared at the end of the oscillator
stabilization delay and begins counting from $0000 again.
The WAIT instruction:
The WAIT instruction has no effect on the COP watchdog.
NOTE:
To prevent a COP timeout during wait mode, exit wait mode periodically
to service the COP.
5.4.4 Timer
The STOP instruction:
Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and
control register, disabling timer interrupt requests and removing
any pending timer interrupt requests
Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately
resumes counting from the last value before the STOP instruction and
continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization
delay, the timer resumes operation from its reset state.
The WAIT instruction:
The WAIT instruction has no effect on the timer.
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