參數(shù)資料
型號： MC68HRC705J1ACDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁數(shù)： 142/162頁
文件大?。?/td> 1517K
代理商： MC68HRC705J1ACDWR2
Technical Data
MC68HC705J1A — Rev. 3.0
80
Low-Power Modes
MOTOROLA
Low-Power Modes
5.4.2 CPU
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the
oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
5.4.3 COP Watchdog
The STOP instruction:
Clears the COP watchdog counter
Disables the COP watchdog clock
NOTE:
To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interrupt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE:
Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
相關(guān)PDF資料
PDF描述
MC68HSC705J1ACDWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HRC705J1ADWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HSR705J1ACDWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC705J1ADWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
MC68HC705J1ADWR2 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
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