參數(shù)資料
型號： MC68HRC05J5AP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁數(shù)： 66/113頁
文件大?。?/td> 1212K
代理商： MC68HRC05J5AP
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
MULTI-FUNCTION TIMER
MC68HC05J5A
8-4
REV 2.1
RTIF - Real Time Interrupt Flag
The RTIF is a read-only ag bit.
1 =
Set when the output of the chosen (1 of 4 selections) Real Time
Interrupt stage goes active. A TIMER Interrupt request will be
generated if RTIE is also set.
0 =
Reset by writing a logical one to the RTIF acknowledge bit, RTIFR.
Writing to the RTIF ag bit has no effect on its value. This bit is
cleared by reset.
TOFE - Timer Overow Enable
The TOFE is an enable bit that allows generation of a TIMER Interrupt upon
overow of the Timer Counter Register.
1 =
When set, the TIMER Interrupt is generated when the TOF ag bit is
set.
0 =
When cleared, no TIMER interrupt caused by TOF bit set will be
generated. This bit is cleared by reset.
RTIE - Real Time Interrupt Enable
The RTIE is an enable bit that allows generation of a TIMER Interrupt by the
RTIF bit.
1 =
When set, the TIMER Interrupt is generated when the RTIF ag bit is
set.
0 =
When cleared, no TIMER interrupt caused by RTIF bit set will be
generated. This bit is cleared by reset.
TOFR - Timer Overow Acknowledge
The TOFR is an acknowledge bit that resets the TOF ag bit. This bit is unaf-
fected by reset. Reading the TOFR will always return a logical zero.
1 =
Clears the TOF ag bit.
0 =
Does not clear the TOF ag bit.
RTIFR - Real Time Interrupt Acknowledge
The RTIFR is an acknowledge bit that resets the RTIF ag bit. This bit is unaf-
fected by reset. Reading the RTIFR will always return a logical zero.
1 =
Clears the RTIF ag bit.
0 =
Does not clear the RTIF ag bit.
RT1, RT0 - Real Time Interrupt Rate Select
The RT0 and RT1 control bits select one of four taps for the Real Time Interrupt
circuit. Table 8-1 shows the available interrupt rates for two fop values. Both the
RT0 and RT1 control bits are set by reset, selecting the lowest periodic rate and
therefore the maximum time in which to alter these bits if necessary. Care
should be taken when altering RT0 and RT1 if the time-out period is imminent
or uncertain. If the selected tap is modied during a cycle in which the counter
is switching, an RTIF could be missed or an additional one could be generated.
To avoid problems, the COP should be cleared just prior to changing RTI taps.
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