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參數(shù)資料
| 型號(hào)： | MC68HRC05J5ADWR2 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDSO20 |
| 封裝： | SOIC-20 |
| 文件頁數(shù)： | 15/106頁 |
| 文件大?。?/td> | 1069K |
| 代理商： | MC68HRC05J5ADWR2 |
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GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
GENERAL DESCRIPTION
MC68HC05J5A
1-6
REV 2.1
1.5.3 RESET
This is an I/O pin. This pin can be used as an input to reset the MCU to a known
start-up state by pulling it to the low state. The RESET pin contains a steering
diode to discharge any voltage on the pin to VDD, when the power is removed. An
internal pull-up is also connected between this pin and VDD. The RESET pin con-
tains an internal Schmitt trigger to improve its noise immunity as an input. This pin
is an output pin if LVR triggers an internal reset.
1.5.4 IRQ (MASKABLE INTERRUPT REQUEST)
This input pin drives the asynchronous IRQ interrupt function of the CPU. The IRQ
interrupt function has a mask option to provide either only negative edge-sensitive
triggering or both negative edge-sensitive and low level-sensitive triggering. If the
option is selected to include level-sensitive triggering, the IRQ input requires an
external resistor to VDD for "wired-OR" operation, if desired. The IRQ pin contains
an internal Schmitt trigger as part of its input to improve noise immunity.
Each of the PA0 through PA3 I/O pins may be connected as an OR function with
the IRQ interrupt function by a mask option. This capability allows keyboard scan
applications where the transitions or levels on the I/O pins will behave the same
as the IRQ pin, except for the inverted phase. The edge or level sensitivity
selected by a separate mask option for the IRQ pin also applies to the I/O pins
OR’ed to create the IRQ signal. Besides, PA7 also has falling-edge only interrupt
capability whose functionality is controlled by another set of register bits.
1.5.5 PA0-PA7
These eight I/O lines comprise Port A. PA6 and PA7 are open-drained pins with
pull-up devices whereas PA0 to PA5 are push-pull pins with pull-down devices.
PA4 to PA7 are also capable of sinking 8mA.
The state of any pin is software programmable and all Port A lines are congured
as inputs during power-on or reset. The lower four I/O pins (PA0 to PA3) can be
connected via an internal OR gate to the IRQ interrupt function enabled by a mask
option. Another independent interrupt source comes from the falling-edge on PA7.
PA7 interrupt source is associated with a second set of interrupt control/status
bits. All Port A pins except PA6 and PA7 have software programmable pull-down
devices also provided by a mask option. PA6 and PA7 pins have software
programmable pull-up devices also provided by the same mask option. Pull-up
devices on PA6 and PA7 once enabled are always enabled regardless of pin
direction conguration, unlike pull-down devices on PA0 to PA5 which are
activated only when these pins are congured as input pins.
PA6 and PA7 pins, when congured as output pins, also have slow output falling-
edge transition feature to reduce EMI. The falling-edge transition time is set at
250ns typical at a specied load of 500pF, assuming the bus rate is 2MHz. The
slow transition output feature of PA6 and PA7, along with that of PB1 and PB2,
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