Timer Interface Module (TIM)
Input/Output Registers
MC68HLC908QY/QT Family — Rev. 2
Data Sheet
MOTOROLA
Timer Interface Module (TIM)
143
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIM CPU interrupt service requests on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation. MSxB
exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and reverts
TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
MSxA — Mode Select Bit A
When ELSxB:A
≠ 00, this read/write bit selects either input capture operation or
unbuffered output compare/PWM operation.
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
When ELSxB:A = 00, this read/write bit selects the initial output level of the
TCHx pin (see Table 14-3). Reset clears the MSxA bit.
1 = Initial output level low
0 = Initial output level high
NOTE:
Before changing a channel function by writing to the MSxB or MSxA bit, set the
TSTOP and TRST bits in the TIM status and control register (TSC).
Table 14-3. Mode, Edge, and Level Selection
MSxB
MSxA
ELSxB
ELSxA
Mode
Configuration
X0
0
Output preset
Pin under port control;
initial output level high
X1
0
Pin under port control;
initial output level low
00
0
1
Input capture
Capture on rising edge only
0
1
0
Capture on falling edge only
00
1
Capture on rising
or falling edge
01
0
Output compare
or PWM
Software compare only
0
1
0
1
Toggle output on compare
0
1
0
Clear output on compare
0
1
Set output on compare
1
X
0
1
Buffered
output
compare or
buffered PWM
Toggle output on compare
1
X
1
0
Clear output on compare
1
X
1
Set output on compare