參數(shù)資料
型號： MC68HCP11A1VFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 42/158頁
文件大小： 776K
代理商： MC68HCP11A1VFN2
MOTOROLA
4-4
PARALLEL I/O
MC68HC11A8
TECHNICAL DATA
4
protocol, reads of port C always return the value sensed at the input to the output buff-
er regardless of the state of the data direction register bits because the lines would not
necessarily have meaningful data on them in the three-state variation of this protocol.
This operation makes it impractical to use some port C lines as static inputs, while us-
ing others as handshake outputs, but does not interfere with the use of some port C
lines as static outputs. Port C lines intended as static outputs or normal handshake
outputs should have their corresponding data direction register bits set, and lines in-
tended as three-state handshake outputs should have their corresponding data direc-
tion register bits clear.
4.5 Parallel I/O Control Register (PIOC)
The parallel handshake l/O functions are available only in the single-chip operating
mode. The PIOC is a read/write register except for bit 7 which is read only.
Table 4-1
shows a summary of handshake l/O operations.
.
NOTE:
1. Set by active edge on STRA
Table 4-1 Handshake l/O Operations Summary
STAI
CWOM
INVB
0
STAF Interrupts
Inhibited
STAF Interrupts
Enabled
Port C Outputs
Normal
Port C Outputs
Open-Drain
STRB Active
Low
STRB Active
High
1
STAF
Clearing
Sequence
1
Read PIOC with
STAF = 1 then
Read PORTCL
HNDS
OIN
PLS
EGA
Port C
Port B
Simple
Strobe
Mode
0
X
X
Inputs latched
into PORTCL
on any active
edge on
STRA.
Inputs latched
into PORTCL
on any active
edge on
STRA.
STRB pulses
on writes to
port B.
Full
Input
Handshake
Read PIOC with
STAF = 1 then
Read PORTCL
1
0
0 = STRB
Active
Level
1 = STRB
Active
Pulse
0 = STRB
Active
Level
1 = STRB
Active
Pulse
Normal out-
put port. Unaf-
fected in
handshake
modes
Full
Output
Handshake
Read PIOC with
STAF = 1 then
Write to
PORTCL
1
1
Driven as out-
puts if STRA at
active level.
Follows DDRC
if STRA not at
active level.
Normal out-
put port. Unaf-
fected in
handshake
modes
7
6
5
4
3
2
1
0
$
1
002
RESET
STAF
0
STAI
0
CWOM
0
HNDS
0
OIN
0
PLS
U
EGA
1
INVB
1
PIOC
0
1
0
1
0
1
STRA
Active Edge
Follow
DDRC
Follow
DDRC
Port C
Driven
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