參數(shù)資料
型號： MC68HCP11A1MFN2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Single-Chip Microcontroller
中文描述： 8-BIT, 2 MHz, MICROCONTROLLER, PQCC52
封裝： PLASTIC, LCC-52
文件頁數(shù)： 71/158頁
文件大?。?/td> 776K
代理商： MC68HCP11A1MFN2
MC68HC11A8
TECHNICAL DATA
PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
MOTOROLA
8-1
8
8 PROGRAMMABLE TIMER, RTI, AND PULSE ACCUMULATOR
This section describes the 16-bit programmable timer, the real time interrupt, and the
pulse accumulator system.
8.1 Programmable Timer
The timer has a single 16-bit free-running counter which is clocked by the output of a
four-stage prescaler (divide by 1, 4, 8, or 16), which is in turn driven by the MCU E
clock. Input functions are called input captures. These input captures record the count
from the free-running counter in response to a detected edge on an input line. Output
functions, called output compares, cause an output action when there is a match be-
tween a 16-bit output-compare register and the free-running counter. This timer sys-
tem has three input capture registers and five output compare registers.
8.1.1 Counter
The key element in the timer system is a 16-bit free-running counter, or timer counter
register. After reset, the MCU is configured to use the E clock as the input to the free-
running counter. Initialization software may optionally reconfigure the system to use
one of the three prescaler values. The prescaler control bits can only be written once
during the first 64 cycles after a reset. Software can read the counter at any time with-
out affecting its value because it is clocked and read during opposite phases of the E
clock.
A counter read should first address the most significant byte. An MPU read of this ad-
dress causes the least significant byte to be transferred to a buffer. This buffer is not
affected by reset and is accessed when reading the least significant byte of the
counter. For double byte read instructions, the two accesses occur on consecutive bus
cycles.
The counter is cleared to $0000 during reset and is a read-only register with one ex-
ception. In test modes only, any MPU write to the most significant byte presets the
counter to $FFF8 regardless of the value involved in the write.
When the count changes from $FFFF to $0000, the timer overflow flag (TOF) bit is set
in timer interrupt flag register 2 (TFLG2). An interrupt can be enabled by setting the
interrupt enable bit (TOI) in timer interrupt mask register 2 (TMSK2).
8.1.2 Input Capture
The input capture registers are 16-bit read-only registers which are not affected by re-
set and are used to latch the value of the counter when a defined transition is sensed
by the corresponding input capture edge detector. The level transition which triggers
counter transfer is defined by the corresponding input edge bits (EDGxB, EDGxA) in
TCTL2.
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