參數(shù)資料
型號(hào)： MC68HCL05P1AP
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝： PLASTIC, DIP-28
文件頁數(shù)： 72/124頁
文件大?。?/td> 623K
代理商： MC68HCL05P1AP
Operating Modes
STOP Instruction
MC68HC05P1A — Rev. 3.0
General Release Specification
MOTOROLA
Operating Modes
51
NON-DISCLOSURE
AGREEMENT
REQUIRED
6.5.0.1 Stop Mode
Execution of the STOP instruction without conversion to halt places the
MCU in its lowest-power consumption mode. In stop mode, the internal
oscillator is turned off, halting
all internal processing, including the COP
watchdog timer. Execution of the STOP instruction automatically clears
the I bit in the condition code register so that the external interrupt is
enabled. All other registers and memory remain unaltered. All
input/output lines remain unchanged.
The MCU can be brought out of stop mode only by an external interrupt
or an externally generated reset. When exiting the stop mode, the
internal oscillator will resume after a 4064 PH2 clock cycle oscillator
stabilization delay.
NOTE:
Execution of the STOP instruction without conversion to halt (via mask
option) will cause the oscillator to stop, and therefore disable the COP
watchdog timer. If the COP watchdog timer is used, the stop mode
should be changed to halt mode by selecting the appropriate mask
option.
6.5.0.2 Halt Mode
Execution of the STOP instruction with the conversion to halt places the
MCU in this low-power mode. Halt mode consumes the same amount of
power as wait mode. (Both halt and wait modes consume more power
than stop mode.)
In halt mode, the PH2 clock is halted, suspending all processor and
internal bus activity. Internal timer clocks remain active, permitting
interrupts to be generated from the 16-bit timer or a reset to be
generated from the COP watchdog timer. Execution of the STOP
instruction automatically clears the I bit in the condition code register,
enabling the external interrupt. All other registers, memory, and
input/output lines remain in their previous states.
If the 16-bit timer interrupt is enabled, the processor will exit halt mode
and resume normal operation. Halt mode also can be exited when an
external interrupt or external reset occurs. When exiting the halt mode,
the PH2 clock will resume after a delay of one to 4064 PH2 clock cycles.
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