參數(shù)資料
型號： MC68HCL05K0DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, MICROCONTROLLER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 108/154頁
文件大?。?/td> 1544K
代理商： MC68HCL05K0DW
Resets
Reset States
MC68HC05K0 MC68HC05K1 — Rev. 2.0
Technical Data
MOTOROLA
Resets
57
5.3.5 Low-Voltage Reset
The low-voltage reset circuit is a mask option that generates a reset
signal if the voltage on the VDD pin falls below the LVR trip point. VDD
must be set at 5 V
±10% if the mask option enabling the low-voltage
reset circuit is selected.
A low-voltage reset pulls the RESET pin low for as long as the
low-voltage condition exists.
NOTE:
When the low-voltage reset is enabled, use a pullup resistor on RESET
because low-voltage reset shorts RESET to ground when it detects a
low VDD. If there is no pullup to limit current, low-voltage reset will short
VDD to ground, causing the chip to possibly remain in reset due to VDD
being pulled down by the short. VDD may also pull current and
permanently damage the chip.
5.4 Reset States
This subsection describes how resets initialize the MCU.
5.4.1 CPU
A reset has these effects on the CPU:
Loads the stack pointer with $FF
Sets the I bit in the condition code register, inhibiting interrupts
Sets the IRQE bit in the interrupt status and control register
Loads the program counter with the user-defined reset vector from
locations $03FE and $03FF
Clears the IRQF bit (IRQ latch)
Clears the stop latch, enabling the CPU clock, or exiting the halt
mode
Clears the wait latch, waking the CPU from wait mode
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