參數(shù)資料
型號： MC68HCL05C9A
廠商： Motorola, Inc.
元件分類： 8位微控制器
英文描述： 8-Bit Microcontroller(8位微控制器)
中文描述： 8位微控制器（8位微控制器）
文件頁數(shù)： 92/160頁
文件大小： 783K
代理商： MC68HCL05C9A
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Serial Peripheral Interface
General Release Specification
MC68HC05C9A
—
Rev. 4.0
92
Serial Peripheral Interface
MOTOROLA
10.4.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in
Figure 10-1
, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line a half cycle before the clock edge (SCK), in order for the slave
device to latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the
operation of the SPI.
10.4.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.The SS line on the master must be tied high. In master
mode, if theSS pin is pulled low during a transmission, a mode fault error
flag (MODF) is set in the SPSR. In master mode the SS pin can be
selected to be a general-purpose output by writing a one in bit 5 of the
port D data direction register, thus disabling the mode fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to V
SS
as long as CPHA = 1 clock modes are used.
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