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參數(shù)資料
| 型號(hào)： | MC68HC912BL16VFU8 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | QFP-64 |
| 文件頁(yè)數(shù)： | 18/128頁(yè) |
| 文件大?。?/td> | 532K |
| 代理商： | MC68HC912BL16VFU8 |
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MOTOROLA
MC68HC912BL16
114
MC68HC912BL16TS/D
Because BDM control logic does not reside in the CPU, BDM hardware commands can be executed
while the CPU is operating normally. The control logic generally uses CPU dead cycles to execute these
commands, but can steal cycles from the CPU when necessary. Other BDM commands are firmware
based, and require the CPU to be in active background mode for execution. While BDM is active, the
CPU executes a firmware program located in a small on-chip ROM that is available in the standard 64-
Kbyte memory map only while BDM is active.
The BDM control logic communicates with an external host development system serially, via the BKGD
pin. This single-wire approach minimizes the number of pins needed for development support.
15.2.1 BDM Serial Interface
The BDM serial interface requires the external controller to generate a falling edge on the BKGD pin to
indicate the start of each bit time. The external controller provides this falling edge whether data is trans-
mitted or received.
BKGD is a pseudo-open-drain pin that can be driven either by an external controller or by the MCU.
Data is transferred MSB first at 16 E-clock cycles per bit (nominal speed). The interface times out if 512
E-clock cycles occur between falling edges from the host. The hardware clears the command register
when this time-out occurs.
The BKGD pin can receive a high or low level or transmit a high or low level. The following diagrams
show timing for each of these cases. Interface timing is synchronous to MCU clocks but asynchronous
to the external host. The internal clock signal is shown for reference in counting cycles.
Figure 28 shows an external host transmitting a logic one or zero to the BKGD pin of a target M68HC12
MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated
falling edge to where the target perceives the beginning of the bit time. Ten target E cycles later, the
target senses the bit level on the BKGD pin. Typically the host actively drives the pseudo-open-drain
BKGD pin during host-to-target transmissions to speed up rising edges. Since the target does not drive
the BKGD pin during this period, there is no need to treat the line as an open-drain signal during host-
to-target transmissions.
Figure 28 BDM Host to Target Serial Bit Timing
HC12A4 BDM HOST TOTARGETTIM
EARLIEST
STARTOF
NEXT BIT
TARGET SENSES BIT
10 CYCLES
SYNCHRONIZATION
UNCERTAINTY
E CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
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