
System Integration Module (SIM)
Data Sheet
MC68HC908QL Family
138
System Integration Module (SIM)
MOTOROLA
13.8.2 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear
status bits while the MCU is in a break state.
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status
registers while the MCU is in a break state. To clear status bits during the break
state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
13.8.3 Break Status Register
The break status register (BSR) contains a flag to indicate that a break caused an
exit from wait mode. This register is only used in emulation mode.
SBSW — SIM Break Stop/Wait
SBSW can be read within the break state SWI routine. The user can modify the
return address on the stack by subtracting one from it.
1 = Wait mode was exited by break interrupt
0 = Wait mode was not exited by break interrupt
Address: $FE03
Bit 7
654321
Bit 0
Read:
BCFE
RRRRRRR
Write:
Reset:
0
R
= Reserved
Figure 13-21. Break Flag Control Register (BFCR)
Address: $FE00
Bit 7
654321
Bit 0
Read:
RRRRRR
SBSW
R
Write:
Note 1
Reset:
0
R
= Reserved
1. Writing a 0 clears SBSW.
Figure 13-22. Break Status Register (BSR)