參數(shù)資料
型號： MC68HC908JL8MFA
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP32
封裝： PLASTIC, LQFP-32
文件頁數(shù)： 17/56頁
文件大?。?/td> 648K
代理商： MC68HC908JL8MFA
MC68HC908JL8SM/D
MC68HC908JL8MC68HC908JK8
TPA
Transfer CCR to A
A
← (CCR)
– – – – – – INH
85
1
TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0 – –
–
DIR
INH
IX1
IX
SP1
3D
4D
5D
6D
7D
9E6D
dd
ff
3
1
3
2
4
TSX
Transfer SP to H:X
H:X
← (SP) + 1
– –– –– – INH
95
2
TXA
Transfer X to A
A
← (X)
– –– –– – INH
9F
1
TXS
Transfer H:X to SP
(SP)
← (H:X) – 1
– – – – – – INH
94
2
A
Accumulator
n
Any bit
C
Carry/borrow bit
opr
Operand (one or two bytes)
CCR
Condition code register
PC
Program counter
dd
Direct address of operand
PCH
Program counter high byte
dd rr
Direct address of operand and relative offset of branch instruction
PCL
Program counter low byte
DD
Direct to direct addressing mode
REL
Relative addressing mode
DIR
Direct addressing mode
rel
Relative program counter offset byte
DIX+
Direct to indexed with post increment addressing mode
rr
Relative program counter offset byte
ee ff
High and low bytes of offset in indexed, 16-bit offset addressing
SP1
Stack pointer, 8-bit offset addressing mode
EXT
Extended addressing mode
SP2
Stack pointer 16-bit offset addressing mode
ff
Offset byte in indexed, 8-bit offset addressing
SP
Stack pointer
H
Half-carry bit
U
Undefined
H
Index register high byte
V
Overflow bit
hh ll
High and low bytes of operand address in extended addressing
X
Index register low byte
I
Interrupt mask
Z
Zero bit
ii
Immediate operand byte
&
Logical AND
IMD
Immediate source to direct destination addressing mode
|
Logical OR
IMM
Immediate addressing mode
⊕
Logical EXCLUSIVE OR
INH
Inherent addressing mode
( )
Contents of
IX
Indexed, no offset addressing mode
–( )
Negation (two’s complement)
IX+
Indexed, no offset, post increment addressing mode
#
Immediate value
IX+D
Indexed with post increment to direct addressing mode
Sign extend
IX1
Indexed, 8-bit offset addressing mode
←
Loaded with
IX1+
Indexed, 8-bit offset, post increment addressing mode
?
If
IX2
Indexed, 16-bit offset addressing mode
:
Concatenated with
M
Memory location
Set or cleared
N
Negative bit
—
Not affected
Table 5. Instruction Set Summary (Sheet 7 of 7)
Source
Form
Operation
Description
Effect
on CCR
Addr
e
s
M
ode
Op
c
ode
Op
e
ra
n
d
Cyc
les
VH I N Z C
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
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I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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