參數(shù)資料
型號: MC68HC908JL8CSPE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封裝: SDIP-32
文件頁數(shù): 21/56頁
文件大?。?/td> 648K
代理商: MC68HC908JL8CSPE
MC68HC908JL8SM/D
MC68HC908JL8MC68HC908JK8
PWM Initialization
Recommended initialization procedure for unbuffered or buffered PWM
signals.
1.
In TSC:
a.
Stop the TIM counter by setting TSTOP.
b.
Reset the TIM counter and prescaler by setting TRST.
2.
Write TMODH:TMODL to set the required PWM period.
3.
Write TCHxH:TCHxL to set the required pulse width.
4.
Write TIM channel x status and control register (TSCx) to select the
desired function:
a.
Write 0:1 (for unbuffered output compare or PWM signals) or 1:0
(for buffered output compare or PWM signals) to the mode select
bits, MSxB:MSxA. See Table 7.
b.
Write 1 to the toggle-on-overflow bit, TOVx.
c.
Write 1:0 (to clear output on compare) or 1:1 (to set output on
compare) to the edge/level select bits, ELSxB:ELSxA. The output
action on compare must force the output to the complement of the
pulse width level. See Table 7.
5.
Clear TSTOP in the TIM status control register (TSC).
TIM Status and
Control Register
TOF — TIM Overflow Flag Bit
TOF is set when the TIM counter reaches the modulo value programmed in
the TIM counter modulo registers. Clear TOF by reading the TIM status and
control register when TOF is set and then writing a logic 0 to TOF.
1 = TIM counter has reached modulo value
TOIE — TIM Overflow Interrupt Enable Bit
1 = TIM overflow interrupts enabled
TSTOP — TIM Stop Bit
1 = TIM counter stopped
TRST — TIM Reset Bit
Setting this write-only bit resets the TIM counter and the TIM prescaler.
TRST is cleared automatically after the TIM counter is reset and always
reads as logic 0.
1 = Prescaler and TIM counter cleared
T1SC: $0020; T2SC: $0030
Bit 7
654321
Bit 0
TOF
TOIE
TSTOP
TRST
0
PS2
PS1
PS0
Reset:
00100000
Figure 20. TIM Status and Control Register (TSC)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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