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參數(shù)資料
型號(hào): MC68HC908JK1ECDW
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 180/180頁(yè)
文件大?。?/td> 0K
描述: IC MCU 1.5K FLASH 8MHZ 20-SOIC
標(biāo)準(zhǔn)包裝: 38
系列: HC08
核心處理器: HC08
芯體尺寸: 8-位
速度: 8MHz
外圍設(shè)備: LED,LVD,POR,PWM
輸入/輸出數(shù): 15
程序存儲(chǔ)器容量: 1.5KB(1.5K x 8)
程序存儲(chǔ)器類(lèi)型: 閃存
RAM 容量: 128 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.3 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x8b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 20-SOIC(0.295",7.50mm 寬)
包裝: 管件
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Interrupts
MC68HC908JL3E Family Data Sheet, Rev. 4
Freescale Semiconductor
99
9.3.2 Voltage Conversion
When the input voltage to the ADC equals VDD, the ADC converts the signal to $FF (full scale). If the input
voltage equals VSS, the ADC converts it to $00. Input voltages between VDD and VSS are a straight-line
linear conversion. All other input voltages will result in $FF if greater than VDD and $00 if less than VSS.
NOTE
Input voltage should not exceed the analog supply voltages.
9.3.3 Conversion Time
Fourteen ADC internal clocks are required to perform one conversion. The ADC starts a conversion on
the first rising edge of the ADC internal clock immediately following a write to the ADSCR. If the ADC
internal clock is selected to run at 1MHz, then one conversion will take 14
μs to complete. With a 1MHz
ADC internal clock the maximum sample rate is 71.43kHz.
9.3.4 Continuous Conversion
In the continuous conversion mode, the ADC continuously converts the selected channel filling the ADC
data register with new data after each conversion. Data from the previous conversion will be overwritten
whether that data has been read or not. Conversions will continue until the ADCO bit is cleared. The
COCO bit (ADC status and control register, $003C) is set after each conversion and can be cleared by
writing the ADC status and control register or reading of the ADC data register.
9.3.5 Accuracy and Precision
The conversion process is monotonic and has no missing codes.
9.4 Interrupts
When the AIEN bit is set, the ADC module is capable of generating a CPU interrupt after each ADC
conversion. A CPU interrupt is generated if the COCO bit is at 0. The COCO bit is not used as a
conversion complete flag when interrupts are enabled.
9.5 Low-Power Modes
The following subsections describe the ADC in low-power modes.
9.5.1 Wait Mode
The ADC continues normal operation during wait mode. Any enabled CPU interrupt request from the ADC
can bring the MCU out of wait mode. If the ADC is not required to bring the MCU out of wait mode, power
down the ADC by setting the ADCH[4:0] bits in the ADC status and control register to 1’s before executing
the WAIT instruction.
14 ADC Clock Cycles
Conversion Time =
ADC Clock Frequency
Number of Bus Cycles = Conversion Time
× Bus Frequency
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