
Timer Interface Module (TIM)
Data Sheet
MC68HC908GZ16
316
Timer Interface Module (TIM)
MOTOROLA
NOTE:
Reset the TIM counter before writing to the TIM counter modulo registers.
23.9.4 TIM Channel Status and Control Registers
Each of the TIM channel status and control registers:
Flags input captures and output compares
Enables input capture and output compare interrupts
Selects input capture, output compare, or PWM operation
Selects high, low, or toggling output on output compare
Selects rising edge, falling edge, or any edge as the active input capture
trigger
Selects output toggling on TIM overflow
Selects 0% and 100% PWM duty cycle
Selects buffered or unbuffered output compare/PWM operation
CHxF — Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set when an
active edge occurs on the channel x pin. When channel x is an output compare
channel, CHxF is set when the value in the TIM counter registers matches the
value in the TIM channel x registers.
Address: T1MODL, $0024 and T2MODL, $002F
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
11111111
Figure 23-8. TIM Counter Modulo Register Low (TMODL)
Address: T1SC0, $0025 and T2SC0, $0030
Bit 7
654321
Bit 0
Read:
CH0F
CH0IE
MS0B
MS0A
ELS0B
ELS0A
TOV0
CH0MAX
Write:
0
Reset:
00000000
Figure 23-9. TIM Channel 0 Status and Control Register (TSC0)
Address: T1SC1, $0028 and T2SC1, $0033
Bit 7
654321
Bit 0
Read:
CH1F
CH1IE
0
MS1A
ELS1B
ELS1A
TOV1
CH1MAX
Write:
0
Reset:
00000000
Figure 23-10. TIM Channel 1 Status and Control Register (TSC1)
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Freescale Semiconductor, Inc.
For More Information On This Product,
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