
Enhanced Serial Communications Interface (ESCI) Module
Functional Description
MC68HC908GR60A MC68HC908GR48A MC68HC908GR32A
Data Sheet
MOTOROLA
Enhanced Serial Communications Interface (ESCI) Module
173
Figure 13-5. ESCI Transmitter
At the start of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of 1s. After the preamble shifts out, control
logic transfers the SCDR data into the transmit shift register. A 0 start bit
automatically goes into the least significant bit (LSB) position of the transmit shift
register. A 1 stop bit goes into the most significant bit (MSB) position.
The ESCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR
transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR
can accept new data from the internal data bus. If the ESCI transmit interrupt
enable bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU
interrupt request.
When the transmit shift register is not transmitting a character, the TxD pin goes to
the idle condition, high. If at any time software clears the ENSCI bit in ESCI control
register 1 (SCC1), the transmitter and receiver relinquish control of the port E pins.
PEN
PTY
H
876543210L
11-BIT
TRANSMIT
STOP
START
T8
SCTE
SCTIE
TCIE
SBK
TC
PARITY
GENERATION
MSB
ESCI DATA REGISTER
LOAD
FROM
SCDR
SHIFT
ENABLE
PREAMBL
E
(ALL
ONES)
BREAK
(AL
LZ
EROS)
TRANSMITTER
CONTROL LOGIC
SHIFT REGISTER
TC
SCTIE
TCIE
SCTE
M
ENSCI
LOOPS
TE
TXINV
INTERNAL BUS
÷ 4
PRE-
SCALER
SCP1
SCP0
SCR1
SCR2
SCR0
BAUD
DIVIDER
÷ 16
SCI_TxD
PR
E-
SCA
LER
PDS1
PDS2
PDS0
PSSB3
PSSB4
PSSB2
PSSB1
PSSB0
LINT
TRANSMITTER CPU
INTERRUPT REQUEST
CGMXCLK
OR
BUS CLOCK