
Serial Peripheral Interface (SPI)
MC68HC908AS32A Data Sheet, Rev. 2.0
208
Freescale Semiconductor
16.4.1 Master Mode
The SPI operates in master mode when the SPI master bit, SPMSTR (SPCR $0010), is set.
NOTE
Configure the SPI modules as master and slave before enabling them.
Enable the master SPI before enabling the slave SPI. Disable the slave SPI
Only a master SPI module can initiate transmissions. Software begins the transmission from a master SPI
module by writing to the SPI data register. If the shift register is empty, the byte immediately transfers to
the shift register, setting the SPI transmitter empty bit, SPTE (SPSCR $0011). The byte begins shifting
out on the MOSI pin under the control of the serial clock. See
Table 16-2.The SPR1 and SPR0 bits control the baud rate generator and determine the speed of the shift register
master also controls the shift register of the slave peripheral.
Figure 16-3. Full-Duplex Master-Slave Connections
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receiver full bit, SPRF (SPSCR), becomes set. At the same
time that SPRF becomes set, the byte from the slave transfers to the receive data register. In normal
operation, SPRF signals the end of a transmission. Software clears SPRF by reading the SPI status and
control register and then reading the SPI data register. Writing to the SPI data register clears the SPTIE
bit.
16.4.2 Slave Mode
The SPI operates in slave mode when the SPMSTR bit (SPCR, $0010) is clear. In slave mode the SPSCK
pin is the input for the serial clock from the master MCU. Before a data transmission occurs, the SS pin
of the slave MCU must be low. SS must remain low until the transmission is complete. See
16.6.2 ModeIn a slave SPI module, data enters the shift register under the control of the serial clock from the master
SPI module. After a byte enters the shift register of a slave SPI, it is transferred to the receive data
register, and the SPRF bit (SPSCR) is set. To prevent an overflow condition, slave software then must
read the SPI data register before another byte enters the shift register.
SHIFT REGISTER
BAUD RATE
GENERATOR
MASTER MCU
SLAVE MCU
VDD
MOSI
MISO
SPSCK
SS