
Standard Timer Module
Block Diagram
Data Sheet
MC68HC812A4 — Rev. 6.0
MOTOROLA
Standard Timer Module
179
12.3 Block Diagram
Figure 12-1. Timer Block Diagram
PRESCALER
CHANNEL 0
PT0
16-BIT COUNTER
MODULE
LOGIC
PR[2:1:0]
DIVIDE-BY-64
MODULE CLOCK
TIMC0H:TIMC0L
EDGE
DETECT
TIMPACNTH:TIMPACNTL
PAOVF
PEDGE
PAOVI
PAMOD
PAE
16-BIT COMPARATOR
TIMCNTH:TIMCNTL
16-BIT LATCH
CHANNEL 1
TIMC1H:TIMC1L
16-BIT COMPARATOR
16-BIT LATCH
16-BIT COUNTER
INTERRUPT
LOGIC
TOF
TOI
C0F
C1F
EDGE
DETECT
PT1
LOGIC
EDGE
DETECT
CxF
CHANNELS 2–6
CHANNEL 7
TIMC7H:TIMC7L
16-BIT COMPARATOR
16-BIT LATCH
C7F
PT7
LOGIC
EDGE
DETECT
IOS0
IOS1
IOS7
OM0
OL0
OM1
OL1
OM7
OL7
EDG1A
EDG1B
EDG7A
EDG7B
EDG0A
EDG0B
TCRE
CHANNEL 7 OUTPUT COMPARE
PAIF
CLEAR COUNTER
PAIF
PAI
INTERRUPT
LOGIC
CxI
INTERRUPT
REQUEST
INTERRUPT
REQUEST
PAOVF
CH. 7 COMPARE
CH. 7 CAPTURE
CH. 1 CAPTURE
MUX
CLK[1:0]
PACLK
PACLK/256
PACLK/65536
PAD
PACLK
PACLK/256
PACLK/65536
TE
CLOCK
CH. 1 COMPARE
CH. 0 COMPARE
CH. 0 CAPTURE
PA INPUT