參數(shù)資料
型號： MC68HC711D0CFB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PQFP44
封裝： 10 X 10 MM, QFP-44
文件頁數(shù)： 107/124頁
文件大?。?/td> 6875K
代理商： MC68HC711D0CFB
SERIAL PERIPHERAL INTERFACE
TECHNICAL DATA
8-5
indicates that an attempt was made to write data to the SPDR while a transfer was in
progress.
When the SPI system is configured as a master and the SS input line goes to active
low, a mode fault error has occurred — usually because two devices have attempted
to act as master at the same time. In cases where more than one device is concurrent-
ly configured as a master, there is a chance of contention between two pin drivers. For
push-pull CMOS drivers, this contention can cause permanent damage. The mode
fault attempts to protect the device by disabling the drivers. The MSTR control bit in
the SPCR and all four DDRD control bits associated with the SPI are cleared. An in-
terrupt is generated subject to masking by the SPIE control bit and the I bit in the CCR.
Other precautions may need to be taken to prevent driver damage. If two devices are
made masters at the same time, mode fault does not help protect either one unless
one of them selects the other as slave. The amount of damage possible depends on
the length of time both devices attempt to act as master.
A write collision error occurs if the SPDR is written while a transfer is in progress. Be-
cause the SPDR is not double buffered in the transmit direction, writes to SPDR cause
data to be written directly into the SPI shift register. Because this write corrupts any
transfer in progress, a write collision error is generated. The transfer continues undis-
turbed, and the write data that caused the error is not written to the shifter.
A write collision is normally a slave error because a slave has no control over when a
master initiates a transfer. A master knows when a transfer is in progress, so there is
no reason for a master to generate a write-collision error, although the SPI logic can
detect write collisions in both master and slave devices.
The SPI configuration determines the characteristics of a transfer in progress. For a
master, a transfer begins when data is written to SPDR and ends when SPIF is set.
For a slave with CPHA equal to zero, a transfer starts when SS goes low and ends
when SS returns high. In this case, SPIF is set at the middle of the eighth SCK cycle
when data is transferred from the shifter to the parallel data register, but the transfer
is still in progress until SS goes high. For a slave with CPHA equal to one, transfer be-
gins when the SCK line goes to its active level, which is the edge at the beginning of
the first SCK cycle. The transfer ends in a slave in which CPHA equals one when SPIF
is set. For a slave, after a byte transfer, SCK must be in inactive state for at least 2 E-
clock cycles before the next byte transfer begins.
8.5 SPI Registers
The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data
storage functions. Refer to the following information for a description of how these reg-
isters are organized.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)PDF資料
PDF描述
MC68HC11D0CP3 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PDIP40
MC68HC711D0CP3 8-BIT, OTPROM, 3 MHz, MICROCONTROLLER, PDIP40
MC68HC11D0CFB3 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
MC68HC711D0CP 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP40
MC68HC11D0CFBE3 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC711D3CFBE2 制造商:Freescale Semiconductor 功能描述:
MC68HC711D3CFN2 功能描述:IC MCU 2MHZ 4K OTP 44-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標(biāo)準(zhǔn)包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
MC68HC711D3CFNE2 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC711D3CFNE3 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
MC68HC711D3VFNE2 功能描述:8位微控制器 -MCU 8B OTP 192RAM 2 MHZ RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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