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| 型號： | MC68HC708MP16 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 8-Bit Microcontroller Units (MCU).(8位微控制器) |
| 中文描述： | 8位微控制器單元（MCU）。（8位微控制器） |
| 文件頁數(shù)： | 5/44頁 |
| 文件大?。?/td> | 342K |
| 代理商： | MC68HC708MP16 |
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Application Note
PWMs Designed for Your System, not Vice Versa
AN1712
MOTOROLA
5
PWMs Designed for Your System, not Vice Versa
As alluded to earlier, a leading cause of frustration and consternation for
motor control design engineers is finding that the pulse width modulator
(PWM) requirements needed for the motor drive are incompatible with
the PWM capabilities of the selected microcontroller. As a result, you're
left with this big hole in the middle of your schematic that needs to be
filled with an assortment of gates and glue and buffers and so on.
The 'MP16 was designed from a system point of view in an effort to
minimize as many of these incompatibilities as possible, while keeping
the cost for this flexibility low. After analyzing many of our customer's
different motor control applications, Motorola soon discovered that a
large number of them had similar requirements which could be
addressed by enhancing the flexibility of the PWM module. Some of the
'MP16 features that account for this flexibility are discussed next.
Living on the Edge or in the Center
The 'MP16 can generate one of two types of PWM signals from the PWM
module at any given time from the PWM module — edge-aligned or
center-aligned — determined by the state of the EDGE bit in the
CONFIG register.
Figure 3
shows both waveform types where the
vertical line represents a waveform alignment reference. The counter
value (represented by the bold traces) is shown being digitally compared
against two levels which are determined by the PWM VALUE registers,
and represent desired pulse widths. The PWM signals shown are the
result of those comparisons. To prevent erroneous pulse widths while
the software is loading new pulse width information, the PWM VALUE
registers are all double buffered. This information is picked up by the
PWM generator at the beginning of every one, two, four, or eight PWM
cycles, determined by how software loads the LDFQ0 and LDFQ1 bits in
PWM control register 2.
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