MC68HC05X16
Rev. 1
MOTOROLA
v
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
9
ANALOG TO DIGITAL CONVERTER
9.1
9.2
9.2.1
9.2.2
9.2.3
9.3
9.4
9.5
A/D converter operation.........................................................................................9-1
A/D registers..........................................................................................................9-3
Port D data register (PORTD)..........................................................................9-3
A/D result data register (ADDATA)...................................................................9-3
A/D status/control register (ADSTAT)...............................................................9-4
A/D converter during STOP mode.........................................................................9-5
A/D converter during WAIT mode..........................................................................9-6
Port D analog input................................................................................................9-6
10
RESETS AND INTERRUPTS
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.4.1
10.1.4.2
10.1.5
10.2
10.2.1
10.2.2
10.2.3
10.2.3.1
10.2.3.2
10.2.3.3
10.2.3.4
10.2.3.5
10.2.4
Resets .................................................................................................................10-1
Power-on reset...............................................................................................10-2
Miscellaneous register..................................................................................10-2
RESET pin.....................................................................................................10-3
Computer operating properly (COP) watchdog reset ....................................10-3
COP watchdog during STOP mode .........................................................10-5
COP watchdog during WAIT mode ..........................................................10-5
Functions affected by reset............................................................................10-5
Interrupts .............................................................................................................10-7
Interrupt priorities...........................................................................................10-9
Nonmaskable software interrupt (SWI)..........................................................10-9
Maskable hardware interrupts........................................................................10-9
Miscellaneous register .............................................................................10-10
External interrupts....................................................................................10-11
MCAN interrupt (CIRQ)............................................................................10-11
Timer interrupts........................................................................................10-12
Serial communications interface (SCI) interrupts.....................................10-12
Hardware controlled interrupt sequence........................................................10-13
11
CPU CORE AND INSTRUCTION SET
11.1
11.1.1
11.1.2
11.1.3
11.1.4
11.1.5
11.2
Registers .............................................................................................................11-1
Accumulator (A).............................................................................................11-1
Index register (X) ...........................................................................................11-2
Program counter (PC)....................................................................................11-2
Stack pointer (SP)..........................................................................................11-2
Condition code register (CCR).......................................................................11-2
Instruction set......................................................................................................11-3