參數(shù)資料
型號(hào)： MC68HC705SR3PE
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 49/96頁(yè)
文件大?。?/td> 0K
描述： IC MCU 3.75K 2.1MHZ OTP 40-DIP
標(biāo)準(zhǔn)包裝： 9
系列： HC05
核心處理器： HC05
芯體尺寸： 8-位
速度： 4MHz
外圍設(shè)備： LED，POR
輸入/輸出數(shù)： 32
程序存儲(chǔ)器容量： 3.75KB（3.75K x 8）
程序存儲(chǔ)器類型： OTP
RAM 容量： 192 x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 4x8b
振蕩器型： 內(nèi)部
工作溫度： 0°C ~ 70°C
封裝/外殼： 40-DIP（0.600"，15.24mm）
包裝： 管件
MC68HC05SR3
Freescale
7-3
ANALOG TO DIGITAL CONVERTER
7
7.2
ADC Status and Control Register (ADSCR)
The ADSCR is a read/write register containing status and control bits for the ADC.
COCO — COnversion COmplete
1 (set)
–
An ADC conversion has completed; ADC Data Register ($0F)
contains valid conversion result.
0 (clear) –
ADC conversion not completed.
This read-only status bit is set when a conversion is completed, indicating that the ADC Data
Register contains a valid result. This COCO bit is cleared either by a write to the ADSCR or a read
of the ADC Data Register. Once the COCO bit is cleared, a new conversion automatically starts.
If the COCO bit is not cleared, conversions are initiated every 32 cycles. In this continuous
conversion mode the ADC Data Register is refreshed with new data, every 32 cycles, and the
COCO bit remains set.
ADRC — ADC RC Oscillator Control
1 (set)
–
ADC uses RC oscillator as clock source.
0 (clear) –
ADC uses internal processor clock as clock source.
The RC oscillator option must be used if the internal processor is running below 1MHz. A
stabilization time of typically 1ms is required when switching to the RC oscillator option.
ADON — ADC On
1 (set)
–
ADC is switched ON.
0 (clear) –
ADC is switched OFF.
When the ADC is turned from OFF to ON, it requires a time tADON for the current sources to
stabilize. During this time ADC conversion results may be inaccurate. Switching the ADC off
disables the internal charge pump and RC oscillator (if selected by ADRC=1), and hence saving
power.
CH2:CH0 — Channel Select Bits
These three bits selects one of eight ADC channels for the conversion. Channels 0 to 3
correspond to inputs AN0-AN3 on port pins PD0-PD3 respectively. Channels 4 and 5 are the ADC
reference inputs VRH and VRL, on port pins PD4 and PD5 respectively. Channels 6 and 7 are used
for internal reference points. Table 7-1 shows the signals selected by the channel select bits.
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
$0E
COCO
ADRC
ADON
CH2
CH1
CH0
000- -000
TPG
51
05SR3.Book Page 3 Thursday, August 4, 2005 1:08 PM
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