參數(shù)資料
型號： MC68HC705SP7S
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
封裝： WINDOWED, CERDIP-28
文件頁數(shù)： 58/108頁
文件大小： 718K
代理商： MC68HC705SP7S
Low-Power Modes
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
58
Freescale Semiconductor
6.3 Effects of Stop and Wait Modes
The STOP and WAIT instructions have the following effects on MCU modules.
6.3.1 Clock Generation
Effects of STOP and WAIT on clock generation are discussed here.
6.3.1.1 STOP
The STOP instruction disables the internal oscillator, stopping the CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral clocks begin running after the oscillator
stabilization delay.
NOTE
The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
6.3.1.2 WAIT
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral clocks immediately begin running.
6.3.2 CPU
Effects of STOP and WAIT on the CPU are discussed here.
6.3.2.1 STOP
The STOP instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling external interrupts
Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator stabilization delay.
After exit from stop mode by external interrupt, the I bit remains clear.
After exit from stop mode by reset, the I bit is set.
6.3.2.2 WAIT
The WAIT instruction:
Clears the interrupt mask (I bit) in the condition code register, enabling interrupts
Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
6.3.3 COP Watchdog
Effects of STOP and WAIT on the COP watchdog are discussed here.
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