參數(shù)資料
型號： MC68HC705SP7CDW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 67/108頁
文件大?。?/td> 718K
代理商： MC68HC705SP7CDW
Port B
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
67
7.3.2 Data Direction Register B
Data direction register B determines whether each port B pin is an input or an output.
DDRB[3:2] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[3:2], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 7-8
shows the I/O logic of port B.
Figure 7-8. Port B I/O Circuitry
Writing a logic 1 to a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0
disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data latch. When bit DDRBx is a
logic 0, reading address $0001 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
Table 7-2
summarizes the operation of the port B pins.
Address:
$0005
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
See Notes
DDRB3
DDRB2
See Note
Write:
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Note:
DDRB5, DDRB4, DDRB1, and DDRB0 should be configured as inputs at all times. These
bits are available for read/write but are not available externally. Configuring them as inputs
will ensure that the pulldown devices are enabled, thus properly terminating them.
Figure 7-7. Data Direction Register B (DDRB)
READ DDRB
WRITE DDRB
RESET
WRITE PORTB
READ PORTB
PBx
I
DDRBx
PBx
PDRBx
SWPDI
100-
μ
A
PULLDOWN
WRITE PDRB
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