參數(shù)資料
型號： MC68HC705SJ7S
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS Microcontroller Unit
中文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封裝： WINDOWED, CERDIP-20
文件頁數(shù)： 63/108頁
文件大?。?/td> 718K
代理商： MC68HC705SJ7S
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
Freescale Semiconductor
63
Chapter 7
Parallel I/O Ports (PORTS)
7.1 Introduction
Ten bidirectional pins form one 8-bit input/output (I/O) port and one 2-bit I/O port. All the bidirectional port
pins are programmable as inputs or outputs.
NOTE
Connect any unused I/O pins to an appropriate logic level, either V
DD
or
V
SS.
Although the I/O ports do not require termination for proper operation,
termination reduces excess current consumption and the possibility of
electrostatic damage.
Addr.
Register Name:
Bit 7
6
5
4
3
2
1
Bit 0
$0000
Port A Data Register (POR-
TA)
See page 64.
Read:
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
Write:
Reset:
Unaffected by reset
$0001
Port B Data Register
(PORTB)
See page 66.
Read:
0
0
See Note
PB3
PB2
See Note
Write:
Reset:
Unaffected by reset
$0004
Data Direction Register A
(DDRA)
See page 64.
Read:
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
Write:
Reset:
0
0
0
0
0
0
0
0
$0005
Data Direction Register B
(DDRB)
See page 67.
Read:
0
0
See Note
DDRB3
DDRB2
See Note
Write:
Reset:
0
0
0
0
0
0
0
0
$0010
Port A Pulldown Register
(PDRA)
See page 65.
Read:
Write:
PDIA7
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
Reset:
0
0
0
0
0
0
0
0
$0011
Port B Pulldown Register
(PDRB)
See page 68.
Read:
Write:
See Note
PDIB3
PDIB2
See Note
Reset:
0
0
0
0
0
0
= Unimplemented
Note:
PB5, PB4, PB1, and PB0 should be configured as inputs at all times. These bits are available for read/write but are not
available externally. Configuring them as inputs will ensure that the pulldown devices are enabled, thus properly termi-
nating them.
Figure 7-1. Parallel I/O Port Register Summary
相關(guān)PDF資料
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