參數(shù)資料
型號: MC68HC705SB7
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝: SOIC-28
文件頁數(shù): 135/170頁
文件大?。?/td> 2161K
代理商: MC68HC705SB7
August 27, 1998
GENERAL RELEASE SPECIFICATION
MC68HC05SB7
16-BIT TIMER
MOTOROLA
REV 2.1
10-5
NOTE
To prevent interrupts from occurring between readings of the ACRH and ACRL,
set the I bit in the condition code register (CCR) before reading ACRH and clear
the I bit after reading ACRL.
10.3
INPUT CAPTURE REGISTERS
Figure 10-6. Timer Input Capture Block Diagram
The input capture function is a means to record the time at which an event occurs.
The source of the event can be selected from the following:
External input via the PB1 pin
CPF ag from the voltage comparator in the analog subsystem
SCL signal from the SMBUS
The input capture source is selected by the TCSEL and ICEN bits.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
MCR
R
TSEN
LVRON
0
SCLK
CSSEL
TCSEL
ESVEN
SMINLEV
$000B
W
COPON
reset:
01000000
Figure 10-7. Miscellaneous Control Register (MCR)
ICIE
ICRH ($0014)
16-BIT COUNTER
÷ 4
INTERNAL
(fOSC ÷ 2)
TIMER CONTROL REG.
TIMER
REQUEST
INPUT CAPTURE (ICF)
RESET
CLOCK
INTERRUPT
ICRL ($0015)
ICF
TIMER STATUS REG.
$0012
$0013
INTERNAL
($FFFC)
DATA
READ
ICRH
READ
ICRL
LATCH
BUS
IEDG
EDGE
SELECT
& DETECT
LOGIC
IEDG
PB1
TCAP
INPUT
SELECT
MUX
CPF
FLAG
ICEN
(bit 4 of $1D)
BIT
INTERNAL
DATA
BUS
TCSEL
(bit 2 of $0B)
SCL
OF
SMBUS
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