參數(shù)資料
型號: MC68HC705P6AMP
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
封裝: PLASTIC, DIP-28
文件頁數(shù): 49/130頁
文件大小: 1541K
代理商: MC68HC705P6AMP
General Description
Functional Pin Description
MC68HC705P6A — Rev. 2.0
Advance Information
MOTOROLA
General Description
25
1.4.7 PD5 and PD7/TCAP
These two I/O pins comprise port D and one of them is shared with the
16-bit timer subsystem. The state of PD5 is software programmable and
is configured as an input during power-on or reset. PD7 is always an
input. It may be read at any time, regardless of which mode of operation
the 16-bit timer is in. Refer to Section 6. Input/Output Ports and
Section 8. Capture/Compare Timer.
1.4.8 TCMP
This pin is the output from the 16-bit timer’s output compare function. It
is low after reset. Refer to Section 8. Capture/Compare Timer.
1.4.9 IRQ/VPP (Maskable Interrupt Request)
This input pin drives the asynchronous interrupt function of the MCU in
user mode and provides the VPP programming voltage in bootloader
mode. The MCU will complete the current instruction being executed
before it responds to the IRQ interrupt request. When the IRQ/VPP pin is
driven low, the event is latched internally to signify an interrupt has been
requested. When the MCU completes its current instruction, the interrupt
latch is tested. If the interrupt latch is set and the interrupt mask bit (I bit)
in the condition code register is clear, the MCU will begin the interrupt
sequence.
Depending on the MOR LEVEL bit, the IRQ/VPP pin will trigger an
interrupt on either a negative edge at the IRQ/VPP pin and/or while the
IRQ/VPP pin is held in the low state. In either case, the IRQ/VPP pin must
be held low for at least one tILIH time period. If the edge- and level-
sensitive mode is selected (LEVEL bit set), the IRQ/VPP input pin
requires an external resistor connected to VDD for wired-OR operation.
If the IRQ/VPP pin is not used, it must be tied to the VDD supply. The
IRQ/VPP pin input circuitry contains an internal Schmitt trigger to improve
noise immunity. Refer to Section 5. Interrupts.
NOTE:
If the voltage level applied to the IRQ/VPP pin exceeds VDD, it may affect
the MCU’s mode of operation. See Section 3. Operating Modes.
相關PDF資料
PDF描述
MC68HC705P6CDW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6P 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP28
MC68HC705P6DW 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
MC68HC705P6S 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
MC68HC705P6CS 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, CDIP28
相關代理商/技術參數(shù)
參數(shù)描述
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