
Serial Communications Interface
SCI Operation
MC68HC705MC4 — Rev. 2.0
General Release Specification
MOTOROLA
Serial Communications Interface
123
NON-DISCLOSURE
AGREEMENT
REQUIRED
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2), and then
writing data to the SCDR, begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
When the shift register is not transmitting a character, the PB4/TDO
(transmit data out) pin goes to the idle condition, logic 1. If software
clears the TE bit during the idle condition and while TDRE is set, the
transmitter relinquishes control of the PB4/TDO pin (acting as a
three-stated input port pin).
11.5.1.3 Break Characters
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
break character. A break character contains all logic 0s and has no start
and stop bits. Break character length depends on the M bit in SCCR1.
As long as SBK is at logic 1, transmitter logic continuously loads break
characters into the shift register. After software clears the SBK bit, the
shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break
character is to guarantee the recognition of the start bit of the next
character.