參數(shù)資料
型號(hào)： MC68HC705KJ1CDW
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： Computer Operation Properly Module
中文描述： 電腦操作正確模塊
文件頁(yè)數(shù)： 36/108頁(yè)
文件大?。?/td> 718K
代理商： MC68HC705KJ1CDW
Central Processor Unit (CPU)
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
36
Freescale Semiconductor
The 10 most significant bits of the stack pointer are permanently fixed at 0000000011, so the stack pointer
produces addresses from $00C0 to $00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins writing over the previously stored data. A
subroutine uses two stack locations; an interrupt uses five locations.
4.5.4 Program Counter
The program counter is a 16-bit register that contains the address of the next instruction or operand to be
fetched. The five most significant bits of the program counter are ignored and appear as 00000.
Normally, the address in the program counter automatically increments to the next sequential memory
location every time an instruction or operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential location.
4.5.5 Condition Code Register
The condition code register is an 8-bit register whose three most significant bits are permanently fixed at
111. The condition code register contains the interrupt mask and four flags that indicate the results of the
instruction just executed.
H — Half-Carry Flag
The CPU sets the half-carry flag when a carry occurs between bits 3 and 4 of the accumulator during
an ADD or ADC operation. The half-carry flag is required for binary-coded decimal (BCD) arithmetic
operations.
I — Interrupt Mask
Setting the interrupt mask disables interrupts. If an interrupt request occurs while the interrupt mask is
logic 0, the CPU saves the CPU registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask is logic 1, the interrupt request
is latched. Normally, the CPU processes the latched interrupt request as soon as the interrupt mask is
cleared again.
A return from interrupt instruction (RTI) unstacks the CPU registers, restoring the interrupt mask to its
cleared state. After any reset, the interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a negative result.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit
0
Reset:
0
0
0
0
0
Loaded with vector from $07FE and $07FF
Figure 4-5. Program Counter (PC)
Bit 7
6
5
4
3
2
1
Bit 0
Read:
1
1
1
H
I
N
Z
C
Write:
Reset:
1
1
1
U
1
U
U
U
= Unimplemented
U = Unaffected
Figure 4-6. Condition Code Register (CCR)
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