參數(shù)資料
型號： MC68HC705K1S
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, CDIP16
封裝： CERAMIC, DIP-16
文件頁數(shù)： 109/140頁
文件大小： 3196K
代理商： MC68HC705K1S
Technical Data
MC68HC705K1 — Rev. 2.0
Parallel Input/Output (I/O)
7.5.2 Data Direction Register B
The contents of data direction register B (DDRB) determine whether
each port B pin is an input or an output. Writing a logic 1 to a DDRB bit
enables the output buffer for the associated port B pin; a logic 0 disables
the output buffer. A reset initializes all DDRB bits to logic 0, configuring
all port B pins as inputs. Setting a DDRB bit to a logic 1 turns off the
pulldown device for that pin.
DDRB1 and DDRB0 — Data Direction Bits 1 and 0
These read/write bits control port B data direction.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
Bit 7–2 — Not Used
Bits 7–2 always read as logic 0s. Writes to these bits have no effect.
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing DDRB bits from logic 0 to logic 1.
7.5.3 Pulldown Register B
Programming the SWPDI bit in the mask option register to a logic 0
enables the port A and port B pulldown devices. The port B pulldown
devices sink approximately 100
A and are under the control of the
PDIB1 and PDIB0 bits in pulldown register B (PDRB). Clearing PDIB1
and PDIB0 turns on the port B pulldown devices if they are configured
as inputs. A pulldown device can be turned on only when its pin is an
input. When SWPDI is a logic 0, reset initializes both port B pins as
inputs with pulldown devices turned on.
Address:
$0005
Bit 7
654321
Bit 0
Read:
000000
DDRB1
DDRB0
Write:
Reset:
00000000
= Unimplemented
Figure 7-6. Data Direction Register B (DDRB)
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
MC68HC705K1DW 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDSO16
MC68HC705K1P 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705L5FU MROM, 4.2 MHz, MICROCONTROLLER, PQFP80
MC68HC05L5FU MROM, 4.2 MHz, MICROCONTROLLER, PQFP80
MC68HC705L5FU 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP80
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC705KJ1CDW 功能描述:8位微控制器 -MCU 8 Bit 4MHz RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC705KJ1CP 功能描述:IC MCU 4MHZ 1.2K OTP 16-DIP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC05 其它有關(guān)文件:STM32F101T8 View All Specifications 特色產(chǎn)品:STM32 32-bit Cortex MCUs 標準包裝:490 系列:STM32 F1 核心處理器:ARM? Cortex?-M3 芯體尺寸:32-位 速度:36MHz 連通性:I²C，IrDA，LIN，SPI，UART/USART 外圍設(shè)備:DMA，PDR，POR，PVD，PWM，溫度傳感器，WDT 輸入/輸出數(shù):26 程序存儲器容量:64KB（64K x 8） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:10K x 8 電壓 - 電源 (Vcc/Vdd):2 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:36-VFQFN，36-VFQFPN 包裝:托盤 配用:497-10030-ND - STARTER KIT FOR STM32497-8853-ND - BOARD DEMO STM32 UNIV USB-UUSCIKSDKSTM32-PL-ND - KIT IAR KICKSTART STM32 CORTEXM3497-8512-ND - KIT STARTER FOR STM32F10XE MCU497-8505-ND - KIT STARTER FOR STM32F10XE MCU497-8304-ND - KIT STM32 MOTOR DRIVER BLDC497-6438-ND - BOARD EVALUTION FOR STM32 512K497-6289-ND - KIT PERFORMANCE STICK FOR STM32MCBSTM32UME-ND - BOARD EVAL MCBSTM32 + ULINK-MEMCBSTM32U-ND - BOARD EVAL MCBSTM32 + ULINK2更多... 其它名稱:497-9032STM32F101T8U6-ND
MC68HC705L32FU 制造商:Rochester Electronics LLC 功能描述: 制造商:Freescale Semiconductor 功能描述:
MC68HC705L5FUE 功能描述:8位微控制器 -MCU 705L5-EPP-80QFP-6019 RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HC705MC4CDW 制造商:Motorola 功能描述:MOTOROLA S7D9B
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*