參數(shù)資料
型號： MC68HC705JJ7S
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封裝： WINDOWED, CERAMIC, DIP-20
文件頁數(shù)： 11/164頁
文件大?。?/td> 1165K
代理商： MC68HC705JJ7S
Programmable Timer
MC68HC705JJ7 MC68HC705JP7 Advance Information Data Sheet, Rev. 4.1
108
Freescale Semiconductor
When the free-running counter rolls over from $FFFF to $0000, the timer overflow flag bit (TOF) is set in
the TSR. When the TOF is set, it can generate an interrupt if the timer overflow interrupt enable bit (TOIE)
is also set in the TCR. The TOF flag bit can only be reset by reading the TMRL after reading the TSR.
Other than clearing any possible TOF flags, reading the TMRH and TMRL in any order or any number of
times does not have any effect on the 16-bit free-running counter.
NOTE
To prevent interrupts from occurring between readings of the TMRH and
TMRL, set the I bit in the condition code register (CCR) before reading
TMRH and clear the I bit after reading TMRL.
11.3 Alternate Counter Registers
The functional block diagram of the 16-bit free-running timer counter and alternate counter registers is
shown in Figure 11-4. The alternate counter registers behave the same as the timer registers, except that
any reads of the alternate counter will not have any effect on the TOF flag bit and timer interrupts. The
alternate counter registers include a transparent buffer latch on the LSB of the 16-bit timer counter.
Figure 11-4. Alternate Counter Block Diagram
The alternate counter registers (ACRH and ACRL) shown in Figure 11-5 are read-only locations which
contain the current high and low bytes of the 16-bit free-running counter. Writing to the alternate counter
registers has no effect. Reset of the device presets the timer counter to $FFFC.
The ACRL latch is a transparent read of the LSB until a read of the ACRH takes place. A read of the ACRH
latches the LSB into the ACRL location until the ACRL is again read. The latched value remains fixed even
Address:
$001A
Bit 7
654321
Bit 0
Read:
Bit 15
14
13
12
11
10
9
Bit 8
Write:
Reset:
11111111
Address:
$001B
Bit 7
654321
Bit 0
Read:
Bit 7
654321
Bit 0
Write:
Reset:
11111100
= Unimplemented
Figure 11-5. Alternate Counter Registers (ACRH and ACRL)
ACRH ($001A)
TMR LSB
16-BIT COUNTER
÷ 4
INTERNAL
(OSC
÷ 2)
RESET
CLOCK
ACRL ($001B)
INTERNAL
$FFFC
DATA
READ
ACRH
READ
ACRL
READ
LATCH
BUS
相關(guān)PDF資料
PDF描述
MC68HC705K1DWR2 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
MC68HC705K1CP 8-BIT, OTPROM, MICROCONTROLLER, PDIP16
MC68HC705K1P 8-BIT, OTPROM, 2 MHz, MICROCONTROLLER, PDIP16
MC68HC705K1DW 8-BIT, OTPROM, MICROCONTROLLER, PDSO16
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