參數(shù)資料
型號(hào)： MC68HC705J5ACDWR2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO20
封裝： SOIC-20
文件頁(yè)數(shù)： 60/106頁(yè)
文件大小： 1069K
代理商： MC68HC705J5ACDWR2
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
MULTI-FUNCTION TIMER
MOTOROLA
REV 2.1
8-5
8.4
OPERATION DURING STOP MODE
The timer system is cleared when going into STOP mode. When STOP is exited
by an external interrupt or an LVR reset or an external RESET, the internal oscilla-
tor will resume, followed by a 224 (or 4064) internal processor oscillator stabilizing
delay. The timer system counter is then cleared and operation resumes. If chosen
by a mask option, the STOP instruction will initiate HALT mode and the effects on
the timer are as described in Section 8.5.
8.5
OPERATION DURING WAIT/HALT MODE
The CPU clock halts during the WAIT/HALT mode, but the timer remains active. If
interrupts are enabled, a timer interrupt or custom periodic interrupt will cause the
processor to exit the WAIT/HALT mode.
Table 8-1. RTI Rates and COP Reset Times
RT1
RT0
RTI Rates at fOP Freq. specified:
Min. COP Reset at fOP Freq. specified:
Divider
1MHz
2MHz
Divider
1MHz
2MHz
00
16384
16.384ms
8.192ms
131072
131ms
66ms
01
32768
32.768ms
16.384ms
262144
262ms
131ms
10
65536
65.536ms
32.768ms
524288
524ms
262ms
11
131072
131.072ms
65.536ms
1048576
1059ms
524ms
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參數(shù)描述
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