參數(shù)資料
型號： MC68HC705J2S
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： HCMOS MICROCONTROLLER UNIT
中文描述： 8-BIT, UVPROM, 2.1 MHz, MICROCONTROLLER, CDIP20
封裝： WINDOWED, CERDIP-20
文件頁數(shù)： 32/82頁
文件大小： 327K
代理商： MC68HC705J2S
MOTOROLA
5-2
RESETS AND INTERRUPTS
MC68HC705J2
Rev. 2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A 4064 t
cyc
(internal clock cycle) delay after the oscillator becomes active allows
the clock generator to stabilize. If the RESET pin is at a logical zero at the end of
4064 t
cyc
, the MCU remains in the reset condition until the signal on theRESET pin
goes to a logical one.
5.1.2 External Reset
A zero applied to the RESET pin for one and one-half t
cyc
generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
5.1.3 Computer Operating Properly (COP) Reset
A timeout of the COP timer generates a COP reset. The COP timer is part of a
software error detection system and must be cleared periodically to start a new
timeout period. (See
7.3 COP Timer
.) To clear the COP timer and prevent a COP
reset, write a zero to bit 0 (COPR) of the COP control register at location $0FF0
before the COP timer times out. The COP control register is a write-only register
that returns the contents of an EPROM location when read. See
Figure 5-1
.
Figure 5-1. COP Control Register
COPR — COP Reset
COPR is a write-only bit. Periodically writing a zero to COPR prevents the COP
timer from resetting the MCU.
5.1.4 Illegal Address Reset
An opcode fetch from an address that is not in the EPROM (locations
$0700–$0EFF), or the RAM ($0090–$00FF) generates an illegal address reset.
COPR —
COP Control Register
$0FF0
Bit 7
—
—
6
—
—
5
—
—
4
—
—
3
—
—
2
—
—
1
—
—
Bit 0
COPR
0
RESET
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