參數(shù)資料
型號(hào)： MC68HC705J2CP
廠商： MOTOROLA INC
元件分類(lèi)： 微控制器/微處理器
英文描述： HCMOS MICROCONTROLLER UNIT
中文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP20
封裝： PLASTIC, DIP-20
文件頁(yè)數(shù)： 19/82頁(yè)
文件大小： 327K
代理商： MC68HC705J2CP
MC68HC705J2
Rev. 2
PARALLEL I/O
MOTOROLA
3-1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
SECTION 3
PARALLEL I/O
This section describes the two bidirectional I/O ports.
3.1 I/O Port Function
The 14 I/O pins form two I/O ports. Each I/O pin is programmable as an input or an
output. The contents of a port data direction register (DDR) determine the data
direction for the port. Writing a 1 to a DDR bit enables the output buffer for the
associated port pin; a 0 disables the output buffer. A reset initializes all implemented
DDR bits to 0, configuring all I/O pins as inputs.
NOTE
Connect any unused inputs and I/O pins to an appropriate logical level,
either V
DD
or V
SS
. Although the I/O ports do not require termination for
proper operation, termination reduces the possibility of electrostatic
damage.
A reset does not initialize the two port data registers. The port data registers for ports
A and B are at addresses $0000 and $0001. To avoid undefined levels, write the data
registers before writing the data direction registers.
With an I/O port pin programmed as an output, reading the pin actually reads the
value of the output data latch and not the voltage on the pin itself. When a pin is
programmed as an input, reading the port bit reads the voltage level on the I/O pin.
The output data latch can always be written, regardless of the state of its DDR bit.
Refer to
Figure 3-1
for typical port circuitry, and to
Table 3-1
for a summary of I/O pin
functions.
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