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參數(shù)資料
| 型號： | MC68HC705G4 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 1 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | QFP-80 |
| 文件頁數(shù)： | 22/128頁 |
| 文件大小： | 290K |
| 代理商： | MC68HC705G4 |
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Page 108
MOTOROLA
Section 10: A/D CONVERTER
MC68HC05G3 (705G4) Specification Rev. 1.1
10.3.2
MULTI-CHANNEL OPERATION
A multiplexer allows the single A/D converter to select one of eight analog signals. The
eight pins of port F are input signals to the multiplexer.
10.4
A/D STATUS AND CONTROL REGISTER (ADSCR) $3B
The following paragraphs describe the function of the A/D status and control register.
Figure 10-1: A/D Status and Control Register
10.4.1
COCO - CONVERSIONS COMPLETE
This read-only status bit is set when a conversion is completed, indicating that the A/D data
register contains valid results. This bit is cleared whenever the A/D status and control
register is written and a new conversion automatically started, or whenever the A/D data
register is read. Once a conversion has been started by writing to the A/D status and control
register, conversions of the selected channel will continue every 32 cycles until the A/D
status and control register is written again. In this continuous conversion mode, the A/D
data register will be filled with new data and the COCO bit will be set every 32 cycles. Data
from the previous conversion will be overwritten regardless of the state of the COCO bit
prior to writing.
10.4.2
ADRC - RC OSCILLATOR ON
When ADRC is set, the A/D section runs on the internal RC oscillator instead of the CPU
clock. The RC oscillator requires a time, t
ADRC = 5s, to stabilize and results can be
inaccurate during this time. If the CPU clock is running below 1 MHz (using OSC, not
XOSC), the RC oscillator must be used. When ADRC is cleared, the A/D uses the CPU
clock.
When the RC oscillator is being used as the conversion clock, three limitations apply:
1. The conversion complete flag (COCO) must be used to determine when
a conversion sequence has been completed, due to the frequency
tolerance of the RC oscillator and its asynchronism with regard to the
MCU E clock.
2. The conversion process runs at the nominal 1.5 MHz rate @ 5 V but the
conversion results must be transferred to the MCU result registers
synchronously with the MCU E clock, so conversion time is limited to a
maximum of one channel per E cycle.
3. If the system clock is running faster than the RC oscillator, the RC
oscillator should be turned off, and the system clock used as the
conversion clock.
COCO
$003B
ADRC ADON
0
CH3
CH2
CH1
CH0
ADSCR
B7
B6
B5
B4
B3
B2
B1
B0
00000000
RESET:
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