參數(shù)資料
型號： MC68HC705E5DW
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDSO28
封裝： SOIC-28
文件頁數(shù)： 139/148頁
文件大?。?/td> 620K
代理商： MC68HC705E5DW
NON-DISCLOSURE
AGREEMENT
REQUIRED
Motorola Bus (M Bus) Interface
General Release Specification
MC68HC705E5 — Rev. 1.0
90
Motorola Bus (M Bus) Interface
MOTOROLA
11.8.3 Software Responses after Transmission or Reception of a Byte
Transmission or reception of a byte will set the data transferring bit
(MCF) to a logic 1, which indicates one byte of communication is
finished. Also, the M-bus interrupt bit (MIF) is set to generate an M-bus
interrupt if the interrupt function is enabled during initialization. Software
must clear the MIF bit in the interrupt routine first. The MCF bit will be
cleared by reading from the M-bus data I/O register (MDR) in receive
mode or writing to MDR in transmit mode. Software may serve the M-bus
I/O in the main program by monitoring the MIF bit if the interrupt function
is disabled.
The following is an example of a software response by a master
transmitter in the interrupt routine. See Figure 11-9.
ISR
BCLR
1,MSR
; CLEAR THE MIF FLAG
BRCLR
5,MCR,SLAVE
; CHECK THE MSTA FLAG,
; BRANCH IF SLAVE MODE
BRCLR
4,MCR,RECEIVE
; CHECK THE MODE FLAG,
; BRANCH IF IN RECEIVE MODE
BRSET
0,MSR,END
; CHECK ACK FROM RECEIVER
; IF NO ACK, END OF
; TRANSMISSION
TRANSMIT LDA
DATABUF
; GET THE NEXT BYTE OF DATA
STA
MDR
; TRANSMIT THE DATA
相關(guān)PDF資料
PDF描述
MC68HC705G1B 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP56
MC68HC705G1FU 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP64
MC68HC05G1B 8-BIT, MROM, 2.1 MHz, MICROCONTROLLER, PDIP56
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MC68HC705J1A 制造商:Freescale Semiconductor 功能描述:
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