
3.3-Vdc Control Timing
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
99
12.8 3.3-Vdc Control Timing
Figure 12-4. TCAP Timing Relationships
Characteristic(1)
1. V
DD = 3.3Vdc ± 0.3 Vdc, VSS = 0 Vdc, TA = –40 to +85°C, unless otherwise noted
Symbol
Min
Max
Unit
Frequency of operation
Crystal
External clock
fOSC
—
DC
2.0
MHz
Internal operating frequency (fOSC ÷ 2)
Crystal
External clock
fOP
—
DC
1.0
MHz
Cycle time
tCYC
1000
—
ns
Crystal oscillator startup time
tOXOV
—100
ms
Stop recovery startup time (crystal oscillator)
tILCH
—100
ms
RESET pulse width
tRL
1.5
—
tCYC
Timer
Resolution(2)
Input capture pulse width
Input capture pulse period
2. Because a 2-bit prescaler in the timer must count four internal cycles (t
CYC), this is the limiting minimum factor in determining
the timer resolution.
tRESL
tTH, tTL
tTLTL
4.0
125
(3)
3. The minimum period t
TLTL should not be less than the number of cycle times it takes to execute the capture interrupt service
routine plus 24 t
CYC.
—
tCYC
ns
tCYC
Interrupt pulse width low (edge-triggered)
tILIH
250
—
ns
Interrupt pulse period
tILIL
(4)
4. The minimum t
ILIL should not be less than the number of cycle times it takes to execute the interrupt service routine plus
19 t
CYC.
—
tCYC
OSC1 pulse width
tOH,tOL
200
—
ns
t
TLTL
*
TCAP PIN
t
TH
*
t
TL
*