參數(shù)資料
型號： MC68HC705C9ACB
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP42
封裝： PLASTIC, SHRINK, DIP-42
文件頁數(shù)： 90/118頁
文件大?。?/td> 750K
代理商： MC68HC705C9ACB
Functional Description
MC68HC05C9A Advance Information Data Sheet, Rev. 4.1
Freescale Semiconductor
73
the SPSR. In master mode the SS pin can be selected to be a general-purpose output (when configured
as an MC68HC05C9A) by writing a 1 in bit 5 of the port D data direction register, thus disabling the mode
fault circuit.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock phase mode, SS must go high
between successive characters in an SPI message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line could be tied to VSS as long as
CPHA = 1 clock modes are used.
10.4 Functional Description
Figure 10-2 shows a block diagram of the serial peripheral interface circuitry. When a master device
transmits data to a slave via the MOSI line, the slave device responds by sending data to the master
device via the master’s MISO line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is replaced by the byte received and
eliminates the need for separate transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the I/O operation has been completed.
Figure 10-2. Serial Peripheral Interface Block Diagram
6
7
543210
SPE
SPIE
SPI CONTROL REGISTER (SPCR)
MSTR
CPOL
CPHA
SPR1
SPR2
$000A
WCOL
SPIF
SPI STATUS REGISTER (SPSR)
0
MODF
0
$000B
BIT 6
BIT 7
SPI DATA REGISTER (SPDR)
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$000C
DWOM
00
SPI SHIFT REGISTER
DIVIDER
CLOCK
LOGIC
SPDR ($000C)
7 6 5 4 3 2 1 0
MODF
WCOL
SPIF
SPR1
SPR0
CPOL
CPHA
MSTR
SPE
SPIE
PD3/
MOSI
PD2/
MISO
÷ 2
÷ 32
÷ 16
÷ 4
SELECT
SPI
CONTROL
INTERNAL DATA BUS
MSTR
S
M
S
M
INTERNAL
CLOCK
(XTAL
÷2)
SPI CLOCK (MASTER)
SPI INTERRUPT REQUEST
SHIFT
CLOCK
PD4/
SCK
PD5/
SS
(SLAVE)
SPI
(MASTER)
CLOCK
相關PDF資料
PDF描述
MC68HC705C9ACFNE 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC705C9AFB 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44
MC68HC705C9AVFN 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQCC44
MC68HC705C9AP 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PDIP40
MC68HC705C9AFB 8-BIT, OTPROM, 2.1 MHz, MICROCONTROLLER, PQFP44
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