
MOTOROLA
C-18
MC68HC05B6
Rev. 4
MC68HC705B5
14
Figure C-10
RAM parallel loader timing diagram
tADR
tDHR
Address
Data
tCR
PD4
tEXR max
tHO
tHI max
PC5 out
PC6 in
tADR max (address to data delay; PC6=PC5)
16 machine cycles
tDHR min (data hold time)
4 machine cycles
tCR (load cycle time; PC6=PC5)
49 machine cycles
tHO (PC5 handshake out delay)
5 machine cycles
tHI max (PC6 handshake in, data hold time)
10 machine cycles
tEXR max (max delay for transition to be
recognised during this cycle; PC6=PC5
30 machine cycles
1 machine cycle = 1/(2f0(Xtal))
TPG
178
05B6Book Page 18 Tuesday, April 6, 1999 8:24 am