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參數(shù)資料
| 型號(hào)： | MC68HC16Z2MPV16 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, MROM, MICROCONTROLLER, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 332/500頁 |
| 文件大?。?/td> | 5695K |
| 代理商： | MC68HC16Z2MPV16 |
MOTOROLA
REGISTER SUMMARY
M68HC16 Z SERIES
D-24
USER’S MANUAL
D.3.2 RAM Test Register
RAMTST — RAM Test Register
$YFFB02
Used for factory test only.
D.3.3 Array Base Address Register High
D.3.4 Array Base Address Register Low
RAMBAH and RAMBAL specify the SRAM array base address in the system memory
map. They can only be written while the SRAM is in low-power stop mode (STOP = 1,
the default out of reset) and the base address lock is disabled (RLCK = 0, the default
out of reset). This prevents accidental remapping of the array. Because the CPU16
drives ADDR[23:20] to the same logic level as ADDR19, the values of RAMBAH
ADDR[23:20] must match the value of ADDR19 for the array to be accessible. These
registers may be read at any time. RAMBAH[15:8] are unimplemented and will always
read zero.
RAMBAH — Array Base Address Register High (Z1, Z2, Z3, and Z4)
$YFFB04
15
8
7
6
5
4
3
2
1
0
NOT USED
ADDR
23
ADDR
22
ADDR
21
ADDR
20
ADDR
19
ADDR
18
ADDR
17
ADDR
16
RESET:
0
RAMBAL — Array Base Address Register Low (1K SRAM — Z1/Z4)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RESET:
0
RAMBAL — Array Base Address Register Low (2K SRAM — Z2)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RESET:
0
RAMBAL — Array Base Address Register Low (4K SRAM — Z3)
$YFFB06
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADDR
15
ADDR
14
ADDR
13
ADDR
12
ADDR
11
ADDR
10
ADDR
9
ADDR
8
ADDR
7
ADDR
6
ADDR
5
ADDR
4
ADDR
3
ADDR
2
ADDR
1
ADDR
0
RESET:
0
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