參數(shù)資料
型號： MC68HC11K4VFU2
廠商： MOTOROLA INC
元件分類： 微控制器/微處理器
英文描述： MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:5.1"; External Width:3"; External Depth:3.9"
中文描述： 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PQFP80
封裝： QFP-80
文件頁數(shù)： 38/80頁
文件大?。?/td> 420K
代理商： MC68HC11K4VFU2
MOTOROLA
38
M68HC11 K Series
MC68HC11KTS/D
5 Resets and Interrupts
All M68HC11 MCUs have three reset vectors and 18 interrupt vectors. The reset vectors are as follows:
RESET, or Power-On Reset
Clock Monitor Fail
COP Failure
The 18 interrupt vectors service 22 interrupt sources (three nonmaskable, 19 maskable). The three non-
maskable interrupt sources are as follows:
XIRQ Pin (X-Bit Interrupt)
Illegal Opcode Trap
Software Interrupt
On-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter-
rupt mask bit (I) in the condition code register (CCR) is clear. Maskable interrupts are prioritized accord-
ing to a default arrangement; however, any one source can be elevated to the highest maskable priority
position by a software-accessible control register (HPRIO). The HPRIO register can be written at any
time, provided bit I in the CCR is set.
Nineteen interrupt sources in the M68HC11 K series devices are subject to masking by the global inter-
rupt mask bit (bit I in the CCR). In addition to the global bit I, all of these sources, except the external
interrupt (IRQ) pin, are controlled by local enable bits in control registers. Most interrupt sources in
M68HC11 devices have separate interrupt vectors; therefore, there is usually no need for software to
poll control registers to determine the cause of an interrupt.
For some interrupt sources, such as the SCI interrupts, the flags are automatically cleared during the
normal course of responding to the interrupt requests. For example, the RDRF flag in the SCI system
is cleared by the automatic clearing mechanism invoked by a read of the SCI status register while RDRF
is set, followed by a read of the SCI data register. The normal response to an RDRF interrupt request
would be to read the SCI status register to check for receive errors, then to read the received data from
the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any
special instructions.
Refer to the following table for a list of interrupt and reset vector assignments.
相關(guān)PDF資料
PDF描述
MC68HC11K1VFU3 MNX Series Enclosure; NEMA Type:1, 2, 4, 4X, 6, 12, 13; Enclosure Material:Polycarbonate; External Height:10"; External Width:7.1"; External Depth:2.5"; Enclosure Color:Light Gray; Approval Bodies:UL, CSA; Cover Color:Light Gray RoHS Compliant: Yes
MC68HC11K4VFU3 Technical Summary 8-Bit Microcontroller
MC68HC11K1VFU4 8-BIT MICROCONTROLLER
MC68HC11K4VFU4 Technical Summary 8-Bit Microcontroller
MC68HC11K4VFN2 Technical Summary 8-Bit Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC11K4VFU3 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary 8-Bit Microcontroller
MC68HC11K4VFU4 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCMOS MICROCONTROLLER UNIT
MC68HC11KA0 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CONFIG Register Programming for EEPROM-based M68HC11 Microcontrollers
MC68HC11KA0CFN2 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
MC68HC11KA0CFN3 制造商:未知廠家 制造商全稱:未知廠家 功能描述:8-Bit Microcontroller
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