
List of Figures
M68HC11K Family
Technical Data
MOTOROLA
List of Figures
19
Figure
Title
Page
6-17
6-18
Port Pullup Assignment Register (PPAR). . . . . . . . . . . . . . . .147
System Configuration Register (CONFIG) . . . . . . . . . . . . . . .147
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
SCI Data Formats. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
SCI Transmitter Block Diagram . . . . . . . . . . . . . . . . . . . . . . .152
SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . .155
SCI Baud Generator Circuit Diagram . . . . . . . . . . . . . . . . . . .157
SCI Baud Rate Control Register High (SCBDH) . . . . . . . . . .158
SCI Baud Rate Control Register Low (SCBDL) . . . . . . . . . . .158
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . .160
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . .161
SCI Status Register 1 (SCSR1) . . . . . . . . . . . . . . . . . . . . . . .162
SCI Status Register 2 (SCSR2) . . . . . . . . . . . . . . . . . . . . . . .164
SCI Data Register (SCDR). . . . . . . . . . . . . . . . . . . . . . . . . . .165
8-1
8-2
8-3
8-4
8-5
8-6
8-7
SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169
Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .171
Serial Peripheral Control Register (SPCR). . . . . . . . . . . . . . .174
Serial Peripheral Status Register (SPSR) . . . . . . . . . . . . . . .176
Serial Peripheral Data Register (SPDR). . . . . . . . . . . . . . . . .177
Port D Data Direction Register (DDRD) . . . . . . . . . . . . . . . . .178
System Configuration Options 2 Register (OPT2) . . . . . . . . .179
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
Timer Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . .183
Capture/Compare Block Diagram. . . . . . . . . . . . . . . . . . . . . .187
Timer Counter Register (TCNT) . . . . . . . . . . . . . . . . . . . . . . .188
Timer Interrupt Flag 2 (TFLG2). . . . . . . . . . . . . . . . . . . . . . . .189
Timer Interrupt Mask 2 (TMSK2) . . . . . . . . . . . . . . . . . . . . . .189
Port A Data Direction Register (DDRA) . . . . . . . . . . . . . . . . .190
Pulse Accumulator Control Register (PACTL) . . . . . . . . . . . .191
Timer Input Capture Registers (TIC1–TIC3). . . . . . . . . . . . . .192
Timer Input Capture 4/Output
Compare 5 Register (TI4/O5) . . . . . . . . . . . . . . . . . . . . . .193
Timer Interrupt Flag 1 Register (TFLG1) . . . . . . . . . . . . . . . .194
Timer Interrupt Mask 1 Register (TMSK1) . . . . . . . . . . . . . . .194
Timer Control 2 Register (TCTL2) . . . . . . . . . . . . . . . . . . . . .195
9-10
9-11
9-12
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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