
MOTOROLA
TIMING SYSTEM
MC68HC11F1
9-14
TECHNICAL DATA
9.4.2 Timer Interrupt Flag Register 2
Bits of this register indicate the occurrence of timer system events. Coupled with the
four high-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate
in either a polled or interrupt driven system. Each bit of TFLG2 corresponds to a bit in
TMSK2 in the same position.
Clear flags by writing a one to the corresponding bit position(s).
TOF — Timer Overflow Interrupt Flag
Set when TCNT changes from $FFFF to $0000
RTIF — Real-Time Interrupt Flag
The RTIF status bit is automatically set to one at the end of every RTI period. To clear
RTIF, write a byte to TFLG2 with bit 6 set.
PAOVF — Pulse Accumulator Overflow Interrupt Flag
PAIF — Pulse Accumulator Input Edge Interrupt Flag
Bits [3:0] — Not implemented
Always read zero
9.4.3 Pulse Accumulator Control Register
Bits RTR[1:0] of this register select the rate for the RTI system. The remaining bits con-
trol the pulse accumulator and IC4/OC5 functions.
Bit 7 — Not implemented
Always reads zero
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
TFLG2 — Timer Interrupt Flag 2
$1025
Bit 7
654321
Bit 0
TOF
RTIF
PAOVF
PAIF
—
RESET:
0000000
0
PACTL — Pulse Accumulator Control
$1026
Bit 7
654321
Bit 0
—
PAEN
PAMOD
PEDGE
—
I4/O5
RTR1
RTR0
RESET:
0000000
0