參數(shù)資料
型號(hào): MC68HC11ED0VFN3
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, 3 MHz, MICROCONTROLLER, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 75/108頁
文件大小: 1672K
代理商: MC68HC11ED0VFN3
Parallel Input/Output (I/O) Ports
Port D Data Direction Register
MC68HC11ED0 — Rev. 1.0
Technical Summary
Parallel Input/Output (I/O) Ports
6.6 Port D Data Direction Register
Refer to Figure 6-4 for a description of the port D data direction register
(DDRD)
Bits [7:6] — Unimplemented
Always read 0
DDD[5:0] — Port D Data Direction Bits
0 = Input
1 = Output
NOTE:
When the serial peripheral interface (SPI) system is in slave mode,
DDD5 has no meaning or effect. When the SPI system is in master
mode, DDD5 determines whether bit 5 of PORTD is an error detect input
(DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI system
is enabled and expects any of bits [4:2] to be an input, that bit will be an
input regardless of the state of the associated DDR bit. If any of bits [4:2]
are expected to be outputs, that bit will be an output only if the
associated DDR bit is set.
Address:
$0009
Bit 7
6
54321
Bit 0
Read:
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Write:
Reset:
00
000000
= Unimplemented
Figure 6-4. Port D Data Direction Register (DDRD)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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