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參數資料
| 型號： | MC68HC11EA9MFN3 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 3 MHz, MICROCONTROLLER, PQCC52 |
| 封裝： | PLASTIC, LCC-52 |
| 文件頁數： | 26/58頁 |
| 文件大?。?/td> | 583K |
| 代理商： | MC68HC11EA9MFN3 |
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MOTOROLA
MC68HC11EA9
32
MC68HC11EA9TS/D
7.1 Phase-Locked Loop Synthesizer
The phase-locked loop synthesizer (PLL) generates clocks for the CPU, bus circuitry, and A/D convert-
er. The clocks for the SCI and timers are derived directly from the EXTAL clock. The EXTAL clock also
provides the reference for the synthesizer which generates a frequency that is a multiple of the EXTAL
clock frequency. Values written to the SYNR register determine the factor by which the EXTAL clock is
scaled. Refer to Figure 8.
The PLL has two frequency bandwidths which are automatically selected whenever AUTO = 1 in the
PLLCR register. When the PLL is first enabled, the wide bandwidth is selected to provide a fast ramp
time. When the desired frequency is nearly reached, the low bandwidth is selected to provide greater
stability. Manual control of bandwidth can be accomplished by clearing the AUTO bit.
Figure 8 Phase-Locked Loop Synthesizer Block Diagram
EA9 PLL BLOCK
CRYSTAL
OSCILLATOR
SYNR
LOOP FILTER
VCO
BUS
CLOCK
SELECT
EXTAL
4XCLK
FOR CPU
AND MEMORIES
MODULE
CLOCK
SELECT
PLLMO
FOR SCI
AND TIMER
MCS
VDDSYN
÷2
SCI
CLOCK
÷4
SYNCHRONIZE
WITH PH2
TIMER
CLOCK
TO TIMER
PRESCALER
PLLTO
÷4
PH2
E
EXTAL
PIN
0 = EXTAL
1 = 4XCLK
BCS
0 = EXTAL
1 = VCOUT
VCOUT
2(Y + 1)(2X)
Y = SYNY[1:0]
X = SYNX[5:0]
XFC
PIN
XTAL
PIN
FREQUENCY
DIVIDER
PHASE
DETECT
VCOUT
PCOMP
EXTAL
TO SCI MODULUS
BAUD GENERATOR
SCI BAUD CLOCK
PHASE-LOCKED
LOOP SYNTHESIZER
EXTERNAL
CRYSTAL
VDDSYN
PIN
XFC
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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