Central Processor Unit (CPU)
Data Sheet
M68HC11E Family — Rev. 5
82
Central Processor Unit (CPU)
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MOTOROLA
BEQ (rel)
BGE (rel)
BGT (rel)
BHI (rel)
Branch if = Zero
Branch if
Zero
Branch if > Zero
Branch if
Higher
Branch if
Higher or Same
Bit(s) Test A
with Memory
Z = 1
N
⊕
V = 0
Z + (N
⊕
V) = 0
C + Z = 0
REL
REL
REL
REL
27
2C
2E
22
rr
rr
rr
rr
3
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BHS (rel)
C = 0
REL
24
rr
3
—
—
—
—
—
—
—
—
BITA (opr)
A M
A
A
A
A
A
B
B
B
B
B
IMM
DIR
EXT
IND,X
IND,Y
IMM
DIR
EXT
IND,X
IND,Y
REL
REL
REL
85
95
B5
A5
A5
C5
D5
F5
E5
E5
2F
25
23
18
ii
dd
hh ll
ff
ff
ii
dd
hh ll
ff
ff
rr
rr
rr
2
3
4
4
5
2
3
4
4
5
3
3
3
—
—
—
—
0
—
BITB (opr)
Bit(s) Test B
with Memory
B M
18
—
—
—
—
0
—
BLE (rel)
BLO (rel)
BLS (rel)
Branch if
Zero
Branch if Lower
Branch if Lower
or Same
Branch if < Zero
Branch if Minus
Branch if not =
Zero
Branch if Plus
Branch Always
Branch if
Bit(s) Clear
Z + (N
⊕
V) = 1
C = 1
C + Z = 1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BLT (rel)
BMI (rel)
BNE (rel)
N
⊕
V = 1
N = 1
Z = 0
REL
REL
REL
2D
2B
26
rr
rr
rr
3
3
3
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BPL (rel)
BRA (rel)
BRCLR(opr)
N = 0
1 = 1
M mm = 0
REL
REL
DIR
IND,X
IND,Y
2A
20
13
1F
1F
rr
rr
dd mm
rr
ff mm
rr
ff mm
rr
rr
dd mm
rr
ff mm
rr
ff mm
rr
dd mm
ff mm
ff mm
rr
3
3
6
7
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(msk)
(rel)
18
BRN (rel)
BRSET(opr)
Branch Never
Branch if Bit(s)
Set
1 = 0
REL
DIR
IND,X
IND,Y
21
12
1E
1E
3
6
7
8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(msk)
(rel)
(M) mm = 0
18
BSET (opr)
(msk)
Set Bit(s)
M + mm
M
DIR
IND,X
IND,Y
REL
14
1C
1C
8D
18
6
7
8
6
—
—
—
—
0
—
BSR (rel)
Branch to
Subroutine
Branch if
Overflow Clear
Branch if
Overflow Set
Compare A to B
Clear Carry Bit
Clear Interrupt
Mask
Clear Memory
Byte
See Figure 3–2
—
—
—
—
—
—
—
—
BVC (rel)
V = 0
REL
28
rr
3
—
—
—
—
—
—
—
—
BVS (rel)
V = 1
REL
29
rr
3
—
—
—
—
—
—
—
—
CBA
CLC
CLI
A – B
0
C
0
I
INH
INH
INH
11
0C
0E
—
—
—
2
2
2
—
—
—
—
—
—
—
—
—
—
—
0
—
—
—
—
—
—
0
—
CLR (opr)
0
M
EXT
IND,X
IND,Y
INH
7F
6F
6F
4F
18
hh ll
ff
ff
6
6
7
2
—
—
—
—
0
1
0
0
CLRA
Clear
Accumulator A
Clear
Accumulator B
Clear Overflow
Flag
0
A
A
—
—
—
—
—
0
1
0
0
CLRB
0
B
B
INH
5F
—
2
—
—
—
—
0
1
0
0
CLV
0
V
INH
0A
—
2
—
—
—
—
—
—
0
—
Table 4-2. Instruction Set (Sheet 2 of 7)
Mnemonic
Operation
Description
Addressing
Mode
Instruction
Operand
Condition Codes
H
I
Opcode
Cycles
S
X
N
Z
V
C
F
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